0|3.6-lite 03:15:52 20041129|User: vsx0 (1001) TCC Start, Command line: tcc -p -e -s /home/tet/test_sets/scen.exec test_sets
5|Linux homestar 2.4.27-1-mckinley-smp #1 SMP Fri Sep 3 12:53:10 MDT 2004 ia64|System Information
20|/home/tet/test_sets/TESTROOT/tetexec.cfg 1|Config Start
30||TEST_MODE=UNIX98
30||TEST_PACKAGES= VSX-PCTS4.4.4 LI18NUX2000-Level1 LSB-FHS2.2 LSB-OS LSB-USERSGROUPS VSTHlite1.0
30||VSXDIR=/home/tet/test_sets/SRC
30||VSX_DBUG_FLAGS=
30||VSX_DBUG_FILE=/home/tet/test_sets/TESTROOT/dbug.out
30||VSX_NAME=LSB Certification Version 2.0.6-2 (ia64)
30||VSX_OPER=Matt Taggart
30||VSX_ORG=Debian
30||VSX_PATH=
30||VSX_SYS=ia64-testing-20041129
30||VSX_UID0=1001
30||VSX_UID1=1002
30||VSX_UID2=1003
30||VSX_GID0=1001
30||VSX_GID1=1002
30||VSX_GID2=1003
30||TET_SIG_IGN=
30||TET_SIG_LEAVE=
30||VSX_CC=/usr/bin/cc
30||VSX_CFLAGS=-ansi -I/usr/include/gdbm
30||VSX_LIBS=-lm  -L/usr/X11R6/lib -L/usr/lib/X11
30||VSX_BLKDEV_FILE=/dev/sda
30||VSX_CHRDEV_FILE=/dev/tty
30||VSX_FCNTL_EDEADLK=Y
30||VSX_FCNTL_MAXLOCK=-1
30||VSX_INVALID_FCNTL_CMD=
30||VSX_INVALID_GID=unsup
30||VSX_INVALID_GNAME=fooxyz
30||VSX_INVALID_PNAME=foopqr
30||VSX_INVALID_UID=unsup
30||VSX_INVALID_WHENCE=-1
30||VSX_INVAL_SIG=-5
30||VSX_MOUNT_DEV=/dev/loop0
30||VSX_NOSPC_DEV=/dev/loop0
30||VSX_PURE_FILE=/home/tet/test_sets/TESTROOT/BIN/purefile
30||VSX_READDIR_EBADF=Y
30||VSX_ROFS=/dev/loop0
30||VSX_SIGSET_EINVAL=Y
30||VSX_SYS_OPEN_MAX=-1
30||VSX_TTYNAME=/dev/pts/1
30||VSX_TTYUSER=vsx0
30||VSX_ULIMIT_BLKS=2
30||VSX_UNLOCKABLE_FILE=unsup
30||VSX_UNUSED_GID=25000
30||VSX_UNUSED_UID=25000
30||VSX_TERMIOS_TTY=/dev/pts/XXX
30||VSX_TERMIOS_LOOP=/dev/pts/XXX
30||VSX_MASTER_TTY=/dev/ptmx
30||VSX_MASTER_LOOP=/dev/ptmx
30||VSX_TERMIOS_ASYNC=N
30||VSX_TERMIOS_BUFFERED=N
30||VSX_TERMIOS_SPEED=B9600
30||VSX_MODEM_CONTROL=N
30||VSX_START_STOP_CHNG=Y
30||VSX_TCGETPGRP_SUPPORTED=Y
30||VSX_TCSETPGRP_SUPPORTED=Y
30||VSX_UNSUPPORTED_CFLAG=none
30||VSX_SUPPORTED_CFLAG=B50
30||PCTS_ECHOE=\b \b
30||PCTS_ECHOK=\025\n
30||VSX_AL_ACCURACY=
30||VSX_CLOCK_ERR=
30||VSX_CLOSEDIR_EBADF=Y
30||VSX_FP_SOFTWARE=
30||VSX_INVALID_AMODE=
30||VSX_INVALID_PC=
30||VSX_INVALID_PGID=
30||VSX_INVALID_SC=
30||VSX_JOB_CONTROL_SUPP=Y
30||VSX_LINK_ACCESS_REQD=Y
30||VSX_LINK_DIR_SUPP=N
30||VSX_LINK_FILESYS_SUPP=N
30||VSX_NONEXEC_FILE=.
30||VSX_OPENDIR_EMNFILE=Y
30||VSX_PRIV_ACCESS_SUPP=Y
30||VSX_PRIV_CHOWN_SUPP=Y
30||VSX_REMOVE_DIR_EBUSY=S
30||VSX_RENAME_DIR_EBUSY=S
30||VSX_RENAME_DIR_WPERM_REQD=N
30||VSX_SAVED_IDS_SUPP=Y
30||VSX_SET_ID_MODES_SUPP=Y
30||VSX_SETPGID_SUPPORTED=Y
30||VSX_UNSUPPORTED_PGID=unsup
30||VSX_INVALID_NL_ITEM=
30||VSX_NXIO_BLKDEV=/home/tet/test_sets/nonexistb
30||VSX_NXIO_CHRDEV=/home/tet/test_sets/nonexistc
30||VSX_BRE_SUBANCHOR=Y
30||VSX_CAT_LOCALE=uk
30||VSX_CODESET1=
30||VSX_CODESET2=
30||VSX_INVALID_CS=
30||VSX_INVALID_POPEN_MODE=z
30||VSX_LINE_BUF_SUPP=T
30||LSB_TEST=Y
30||LSB_BIN_SHELL_BASH=true
30||LSB_C_SHELL_SUPP=true
30||LSB_KERNEL_NAME=vmlinuz-2.4.27-1-mckinley-smp
30||LSB_USER_DEV_CREAT=
30||LSB_FILE_ASCII=
30||LSB_FILE_MAGIC=
30||LSB_FILE_TERMCAP=
30||LBS_FILE_TERMCAPDB=
30||LSB_PROCESS_ACCOUNTING=
30||LSB_C_COMPILER_SUPPORTED=true
30||LSB_NIS_SUPPORTED=
30||LSB_LOCALE_SOURCE=/home/tet/LSB.tools/li18nux_psldefs/LTP_1
30||LSB_CHARMAP_SOURCE=/home/tet/LSB.tools/li18nux_psldefs/UTF-8
30||LI18NUX_FONT_DIR=/home/tet/LSB.tools/li18nux_font
30||LI18NUX_FONT_PORT=9999
30||VSRT_CFLAGS=-D_REENTRANT
30||VSRT_LIBS=-lrt -lpthread -lc
30||VSRT_RT_LIB=-lrt
30||VSRT_SUPPORTS_RT_FG=y
30||VSRT_MQUEUE_IS_DISTINCT=n
30||VSRT_SEM_IS_DISTINCT=n
30||VSRT_SHM_IS_DISTINCT=n
30||VSRT_MQDES_IS_FILEDES=n
30||VSRT_MQUEUE_PREFIX=/
30||VSRT_MQUEUE_PREFIX_INVALID=./
30||VSRT_SHM_PREFIX=/
30||VSRT_SHM_PREFIX_INVALID=./
30||VSRT_SEM_IS_FILEDES=n
30||VSRT_SEM_PREFIX=/
30||VSRT_SEM_PREFIX_INVALID=./
30||VSRT_FILE_NO_MMAP=
30||VSRT_FILE_ASYNC_IO=/tmp/vsrt_aio_file
30||VSRT_FILE_NO_ASYNC_IO=
30||VSRT_TERMIOS_TTY=
30||VSRT_TERMIOS_LOOP=
30||VSRT_MASTER_PTY=/dev/ptmx
30||VSRT_FILE_SYNC_IO=
30||VSRT_FILE_NO_SYNC_IO=
30||VSRT_FILE_PRIO_IO=
30||VSRT_FILE_NO_PRIO_IO=
30||VSRT_RELAX_WRITE_ORDER=n
30||VSRT_INVALID_AIO_NBYTES_READ=
30||VSRT_ADDR_SPACE_PAGES=34446794752
30||VSRT_MMAP_UNSUPPORTED_PROT=0
30||VSRT_BAD_CLOCKID=2048
30||VSRT_REALTIME_RES_SEC=0
30||VSRT_REALTIME_RES_NSEC=1000
30||VSRT_DEF_TIMER_SIG=15
30||VSRT_RT_SIG_DEF_IGN=28
30||VSRT_SCHED_INVALID=-1
30||VSRT_SUPPORTS_AIO_CANCEL=y
30||VSRT_SUPPORTS_AIO_ERROR=y
30||VSRT_SUPPORTS_AIO_FSYNC=y
30||VSRT_SUPPORTS_AIO_READ=y
30||VSRT_SUPPORTS_AIO_RETURN=y
30||VSRT_SUPPORTS_AIO_SUSPEND=y
30||VSRT_SUPPORTS_AIO_WRITE=y
30||VSRT_SUPPORTS_LIO_LISTIO=y
30||VSRT_SUPPORTS_MLOCKALL=y
30||VSRT_SUPPORTS_MUNLOCKALL=y
30||VSRT_SUPPORTS_MLOCK=y
30||VSRT_SUPPORTS_MUNLOCK=y
30||VSRT_SUPPORTS_MPROTECT=y
30||VSRT_SUPPORTS_MMAP=y
30||VSRT_SUPPORTS_MUNMAP=y
30||VSRT_SUPPORTS_FTRUNCATE=y
30||VSRT_SUPPORTS_MSYNC=y
30||VSRT_SUPPORTS_MQ_CLOSE=y
30||VSRT_SUPPORTS_MQ_GETATTR=y
30||VSRT_SUPPORTS_MQ_NOTIFY=y
30||VSRT_SUPPORTS_MQ_OPEN=y
30||VSRT_SUPPORTS_MQ_RECEIVE=y
30||VSRT_SUPPORTS_MQ_SEND=y
30||VSRT_SUPPORTS_MQ_SETATTR=y
30||VSRT_SUPPORTS_MQ_UNLINK=y
30||VSRT_SUPPORTS_PTHREAD_GETSCHEDPARAM=y
30||VSRT_SUPPORTS_PTHREAD_ATTR_SETINHERITSCHED=y
30||VSRT_SUPPORTS_PTHREAD_ATTR_SETSCHEDPOLICY=y
30||VSRT_SUPPORTS_PTHREAD_ATTR_SETSCOPE=y
30||VSRT_SUPPORTS_SCHED_GET_PRIORITY_MAX=y
30||VSRT_SUPPORTS_SCHED_GET_PRIORITY_MIN=y
30||VSRT_SUPPORTS_SCHED_GET_PARAM=y
30||VSRT_SUPPORTS_SCHED_GETSCHEDULER=y
30||VSRT_SUPPORTS_SCHED_RR_GET_INTERVAL=y
30||VSRT_SUPPORTS_SCHED_SETPARAM=y
30||VSRT_SUPPORTS_SCHED_SETSCHEDULER=y
30||VSRT_SUPPORTS_SCHED_YIELD=y
30||VSRT_SUPPORTS_SIGQUEUE=y
30||VSRT_SUPPORTS_SIGTIMEDWAIT=y
30||VSRT_SUPPORTS_SIGWAITINFO=y
30||VSRT_SUPPORTS_SEM_CLOSE=y
30||VSRT_SUPPORTS_SEM_DESTROY=y
30||VSRT_SUPPORTS_SEM_GETVALUE=y
30||VSRT_SUPPORTS_SEM_INIT=y
30||VSRT_SUPPORTS_SEM_OPEN=y
30||VSRT_SUPPORTS_SEM_POST=y
30||VSRT_SUPPORTS_SEM_TRYWAIT=y
30||VSRT_SUPPORTS_SEM_UNLINK=y
30||VSRT_SUPPORTS_SEM_WAIT=y
30||VSRT_SUPPORTS_FDATASYNC=y
30||VSRT_SUPPORTS_SHM_OPEN=y
30||VSRT_SUPPORTS_SHM_UNLINK=y
30||VSRT_SUPPORTS_CLOCK_GETRES=y
30||VSRT_SUPPORTS_CLOCK_GETTIME=y
30||VSRT_SUPPORTS_CLOCK_SETTIME=y
30||VSRT_SUPPORTS_NANOSLEEP=y
30||VSRT_SUPPORTS_TIMER_CREATE=y
30||VSRT_SUPPORTS_TIMER_DELETE=y
30||VSRT_SUPPORTS_TIMER_GETOVERRUN=y
30||VSRT_SUPPORTS_TIMER_GETTIME=y
30||VSRT_SUPPORTS_TIMER_SETTIME=y
30||VSTH_CFLAGS=
30||VSTH_LIBS=-lpthread
30||VSTH_VALID_GUARDSIZE=
30||VSTH_INVALID_GUARDSIZE=
30||VSTH_VALID_STACKSIZE=196608
30||VSTH_INVALID_STACKSIZE=512
30||VSTH_UPAO_EINVAL=N
30||VSTH_SIG_IGN=
30||VSTH_SELF_EDEADLK_DETECTED=Y
30||VSTH_REFERENTIAL_EDEADLK_DETECTED=Y
30||VSTH_DETACH_EINVAL=Y
30||VSTH_TID_ESRCH=Y
30||VSTH_SIG_EINVAL=Y
30||VSTH_INVALID_SIG=100
30||VSTH_UNSUPPORTED_SIG=100
30||VSTH_PS_EINVAL=
30||VSTH_PSHARED_EINVAL=
30||VSTH_TID_EINVAL=Y
30||VSTH_GETLOGIN_R_ERANGE=Y
30||VSTH_TTYNAME_R_ENOTTY=Y
30||VSTH_TTYNAME_R_ERANGE=Y
30||VSTH_READDIR_R_EBADF=Y
30||VSTH_ICONV_CODESET1=
30||VSTH_ICONV_CODESET2=
30||VSTH_SUPP_GID=504
30||TET_EXEC_IN_PLACE=True
30||TET_OUTPUT_CAPTURE=False
30||TET_API_COMPLIANT=True
30||TET_PASS_TC_NAME=False
30||TET_VERSION=3.6-lite
40||Config End
70||"total tests in ANSI.os 1536"
10|0 /tset/ANSI.os/charhandle/Misalnum/T.isalnum 03:15:52|TC Start, scenario ref 2-0
15|0 3.6-lite 2|TCM Start
400|0 1 1 03:15:52|IC Start
200|0 1 03:15:52|TP Start
220|0 1 0 03:15:52|PASS
410|0 1 1 03:15:52|IC End
400|0 2 1 03:15:52|IC Start
200|0 2 03:15:52|TP Start
220|0 2 0 03:15:52|PASS
410|0 2 1 03:15:52|IC End
80|0 0 03:15:53|TC End, scenario ref 2-0
10|1 /tset/ANSI.os/charhandle/Misalnum_X/T.isalnum_X 03:15:53|TC Start, scenario ref 3-0
15|1 3.6-lite 1|TCM Start
400|1 1 1 03:15:53|IC Start
200|1 1 03:15:53|TP Start
220|1 1 0 03:15:53|PASS
410|1 1 1 03:15:53|IC End
80|1 0 03:15:54|TC End, scenario ref 3-0
10|2 /tset/ANSI.os/charhandle/Misalpha/T.isalpha 03:15:54|TC Start, scenario ref 4-0
15|2 3.6-lite 2|TCM Start
400|2 1 1 03:15:54|IC Start
200|2 1 03:15:54|TP Start
220|2 1 0 03:15:54|PASS
410|2 1 1 03:15:54|IC End
400|2 2 1 03:15:54|IC Start
200|2 2 03:15:54|TP Start
220|2 2 0 03:15:54|PASS
410|2 2 1 03:15:54|IC End
80|2 0 03:15:55|TC End, scenario ref 4-0
10|3 /tset/ANSI.os/charhandle/Misalpha_X/T.isalpha_X 03:15:55|TC Start, scenario ref 5-0
15|3 3.6-lite 1|TCM Start
400|3 1 1 03:15:55|IC Start
200|3 1 03:15:55|TP Start
220|3 1 0 03:15:55|PASS
410|3 1 1 03:15:55|IC End
80|3 0 03:15:56|TC End, scenario ref 5-0
10|4 /tset/ANSI.os/charhandle/Miscntrl/T.iscntrl 03:15:56|TC Start, scenario ref 6-0
15|4 3.6-lite 2|TCM Start
400|4 1 1 03:15:56|IC Start
200|4 1 03:15:56|TP Start
220|4 1 0 03:15:56|PASS
410|4 1 1 03:15:56|IC End
400|4 2 1 03:15:56|IC Start
200|4 2 03:15:56|TP Start
220|4 2 0 03:15:56|PASS
410|4 2 1 03:15:56|IC End
80|4 0 03:15:57|TC End, scenario ref 6-0
10|5 /tset/ANSI.os/charhandle/Miscntrl_X/T.iscntrl_X 03:15:57|TC Start, scenario ref 7-0
15|5 3.6-lite 1|TCM Start
400|5 1 1 03:15:57|IC Start
200|5 1 03:15:57|TP Start
220|5 1 0 03:15:57|PASS
410|5 1 1 03:15:57|IC End
80|5 0 03:15:58|TC End, scenario ref 7-0
10|6 /tset/ANSI.os/charhandle/Misdigit/T.isdigit 03:15:58|TC Start, scenario ref 8-0
15|6 3.6-lite 1|TCM Start
400|6 1 1 03:15:58|IC Start
200|6 1 03:15:58|TP Start
220|6 1 0 03:15:58|PASS
410|6 1 1 03:15:58|IC End
80|6 0 03:15:59|TC End, scenario ref 8-0
10|7 /tset/ANSI.os/charhandle/Misgraph/T.isgraph 03:15:59|TC Start, scenario ref 9-0
15|7 3.6-lite 2|TCM Start
400|7 1 1 03:15:59|IC Start
200|7 1 03:15:59|TP Start
220|7 1 0 03:15:59|PASS
410|7 1 1 03:15:59|IC End
400|7 2 1 03:15:59|IC Start
200|7 2 03:15:59|TP Start
220|7 2 0 03:15:59|PASS
410|7 2 1 03:15:59|IC End
80|7 0 03:16:00|TC End, scenario ref 9-0
10|8 /tset/ANSI.os/charhandle/Misgraph_X/T.isgraph_X 03:16:00|TC Start, scenario ref 10-0
15|8 3.6-lite 1|TCM Start
400|8 1 1 03:16:00|IC Start
200|8 1 03:16:00|TP Start
220|8 1 0 03:16:00|PASS
410|8 1 1 03:16:00|IC End
80|8 0 03:16:01|TC End, scenario ref 10-0
10|9 /tset/ANSI.os/charhandle/Mislower/T.islower 03:16:01|TC Start, scenario ref 11-0
15|9 3.6-lite 2|TCM Start
400|9 1 1 03:16:01|IC Start
200|9 1 03:16:01|TP Start
220|9 1 0 03:16:01|PASS
410|9 1 1 03:16:01|IC End
400|9 2 1 03:16:01|IC Start
200|9 2 03:16:01|TP Start
220|9 2 0 03:16:01|PASS
410|9 2 1 03:16:01|IC End
80|9 0 03:16:02|TC End, scenario ref 11-0
10|10 /tset/ANSI.os/charhandle/Mislower_X/T.islower_X 03:16:02|TC Start, scenario ref 12-0
15|10 3.6-lite 1|TCM Start
400|10 1 1 03:16:02|IC Start
200|10 1 03:16:02|TP Start
220|10 1 0 03:16:02|PASS
410|10 1 1 03:16:02|IC End
80|10 0 03:16:03|TC End, scenario ref 12-0
10|11 /tset/ANSI.os/charhandle/Misprint/T.isprint 03:16:03|TC Start, scenario ref 13-0
15|11 3.6-lite 2|TCM Start
400|11 1 1 03:16:03|IC Start
200|11 1 03:16:03|TP Start
220|11 1 0 03:16:03|PASS
410|11 1 1 03:16:03|IC End
400|11 2 1 03:16:03|IC Start
200|11 2 03:16:03|TP Start
220|11 2 0 03:16:03|PASS
410|11 2 1 03:16:03|IC End
80|11 0 03:16:04|TC End, scenario ref 13-0
10|12 /tset/ANSI.os/charhandle/Misprint_X/T.isprint_X 03:16:04|TC Start, scenario ref 14-0
15|12 3.6-lite 1|TCM Start
400|12 1 1 03:16:04|IC Start
200|12 1 03:16:04|TP Start
220|12 1 0 03:16:04|PASS
410|12 1 1 03:16:04|IC End
80|12 0 03:16:05|TC End, scenario ref 14-0
10|13 /tset/ANSI.os/charhandle/Mispunct/T.ispunct 03:16:05|TC Start, scenario ref 15-0
15|13 3.6-lite 2|TCM Start
400|13 1 1 03:16:05|IC Start
200|13 1 03:16:05|TP Start
220|13 1 0 03:16:05|PASS
410|13 1 1 03:16:05|IC End
400|13 2 1 03:16:05|IC Start
200|13 2 03:16:05|TP Start
220|13 2 0 03:16:05|PASS
410|13 2 1 03:16:05|IC End
80|13 0 03:16:06|TC End, scenario ref 15-0
10|14 /tset/ANSI.os/charhandle/Mispunct_X/T.ispunct_X 03:16:06|TC Start, scenario ref 16-0
15|14 3.6-lite 1|TCM Start
400|14 1 1 03:16:06|IC Start
200|14 1 03:16:06|TP Start
220|14 1 0 03:16:06|PASS
410|14 1 1 03:16:06|IC End
80|14 0 03:16:07|TC End, scenario ref 16-0
10|15 /tset/ANSI.os/charhandle/Misspace/T.isspace 03:16:07|TC Start, scenario ref 17-0
15|15 3.6-lite 2|TCM Start
400|15 1 1 03:16:07|IC Start
200|15 1 03:16:07|TP Start
220|15 1 0 03:16:07|PASS
410|15 1 1 03:16:07|IC End
400|15 2 1 03:16:07|IC Start
200|15 2 03:16:07|TP Start
220|15 2 0 03:16:07|PASS
410|15 2 1 03:16:07|IC End
80|15 0 03:16:08|TC End, scenario ref 17-0
10|16 /tset/ANSI.os/charhandle/Misspace_X/T.isspace_X 03:16:08|TC Start, scenario ref 18-0
15|16 3.6-lite 1|TCM Start
400|16 1 1 03:16:08|IC Start
200|16 1 03:16:08|TP Start
220|16 1 0 03:16:08|PASS
410|16 1 1 03:16:08|IC End
80|16 0 03:16:09|TC End, scenario ref 18-0
10|17 /tset/ANSI.os/charhandle/Misupper/T.isupper 03:16:09|TC Start, scenario ref 19-0
15|17 3.6-lite 2|TCM Start
400|17 1 1 03:16:09|IC Start
200|17 1 03:16:09|TP Start
220|17 1 0 03:16:09|PASS
410|17 1 1 03:16:09|IC End
400|17 2 1 03:16:09|IC Start
200|17 2 03:16:09|TP Start
220|17 2 0 03:16:09|PASS
410|17 2 1 03:16:09|IC End
80|17 0 03:16:10|TC End, scenario ref 19-0
10|18 /tset/ANSI.os/charhandle/Misupper_X/T.isupper_X 03:16:10|TC Start, scenario ref 20-0
15|18 3.6-lite 1|TCM Start
400|18 1 1 03:16:10|IC Start
200|18 1 03:16:10|TP Start
220|18 1 0 03:16:10|PASS
410|18 1 1 03:16:10|IC End
80|18 0 03:16:11|TC End, scenario ref 20-0
10|19 /tset/ANSI.os/charhandle/Misxdigit/T.isxdigit 03:16:11|TC Start, scenario ref 21-0
15|19 3.6-lite 1|TCM Start
400|19 1 1 03:16:11|IC Start
200|19 1 03:16:11|TP Start
220|19 1 0 03:16:11|PASS
410|19 1 1 03:16:11|IC End
80|19 0 03:16:12|TC End, scenario ref 21-0
10|20 /tset/ANSI.os/charhandle/Mtolower/T.tolower 03:16:12|TC Start, scenario ref 22-0
15|20 dummy 1|TCM Start
400|20 1 3 03:16:12|IC Start
200|20 1 03:16:12|TP Start
520|20 1 2165 1 1|No macros defined or no macro tests required
220|20 1 3 03:16:12|NOTINUSE
200|20 2 03:16:12|TP Start
520|20 2 2165 1 1|No macros defined or no macro tests required
220|20 2 3 03:16:12|NOTINUSE
200|20 3 03:16:12|TP Start
520|20 3 2165 1 1|No macros defined or no macro tests required
220|20 3 3 03:16:12|NOTINUSE
410|20 1 3 03:16:12|IC End
80|20 0 03:16:13|TC End, scenario ref 22-0
10|21 /tset/ANSI.os/charhandle/Mtolower_X/T.tolower_X 03:16:13|TC Start, scenario ref 23-0
15|21 dummy 1|TCM Start
400|21 1 1 03:16:13|IC Start
200|21 1 03:16:13|TP Start
520|21 1 2168 1 1|No macros defined or no macro tests required
220|21 1 3 03:16:13|NOTINUSE
410|21 1 1 03:16:13|IC End
80|21 0 03:16:14|TC End, scenario ref 23-0
10|22 /tset/ANSI.os/charhandle/Mtoupper/T.toupper 03:16:14|TC Start, scenario ref 24-0
15|22 dummy 1|TCM Start
400|22 1 3 03:16:14|IC Start
200|22 1 03:16:14|TP Start
520|22 1 2171 1 1|No macros defined or no macro tests required
220|22 1 3 03:16:14|NOTINUSE
200|22 2 03:16:14|TP Start
520|22 2 2171 1 1|No macros defined or no macro tests required
220|22 2 3 03:16:14|NOTINUSE
200|22 3 03:16:14|TP Start
520|22 3 2171 1 1|No macros defined or no macro tests required
220|22 3 3 03:16:14|NOTINUSE
410|22 1 3 03:16:14|IC End
80|22 0 03:16:15|TC End, scenario ref 24-0
10|23 /tset/ANSI.os/charhandle/Mtoupper_X/T.toupper_X 03:16:15|TC Start, scenario ref 25-0
15|23 dummy 1|TCM Start
400|23 1 1 03:16:15|IC Start
200|23 1 03:16:15|TP Start
520|23 1 2174 1 1|No macros defined or no macro tests required
220|23 1 3 03:16:15|NOTINUSE
410|23 1 1 03:16:15|IC End
80|23 0 03:16:16|TC End, scenario ref 25-0
10|24 /tset/ANSI.os/charhandle/isalnum/T.isalnum 03:16:16|TC Start, scenario ref 26-0
15|24 3.6-lite 2|TCM Start
400|24 1 1 03:16:16|IC Start
200|24 1 03:16:16|TP Start
220|24 1 0 03:16:16|PASS
410|24 1 1 03:16:16|IC End
400|24 2 1 03:16:16|IC Start
200|24 2 03:16:16|TP Start
220|24 2 0 03:16:16|PASS
410|24 2 1 03:16:16|IC End
80|24 0 03:16:17|TC End, scenario ref 26-0
10|25 /tset/ANSI.os/charhandle/isalnum_X/T.isalnum_X 03:16:17|TC Start, scenario ref 27-0
15|25 3.6-lite 1|TCM Start
400|25 1 1 03:16:17|IC Start
200|25 1 03:16:17|TP Start
220|25 1 0 03:16:17|PASS
410|25 1 1 03:16:17|IC End
80|25 0 03:16:18|TC End, scenario ref 27-0
10|26 /tset/ANSI.os/charhandle/isalpha/T.isalpha 03:16:18|TC Start, scenario ref 28-0
15|26 3.6-lite 2|TCM Start
400|26 1 1 03:16:18|IC Start
200|26 1 03:16:18|TP Start
220|26 1 0 03:16:18|PASS
410|26 1 1 03:16:18|IC End
400|26 2 1 03:16:18|IC Start
200|26 2 03:16:18|TP Start
220|26 2 0 03:16:18|PASS
410|26 2 1 03:16:18|IC End
80|26 0 03:16:19|TC End, scenario ref 28-0
10|27 /tset/ANSI.os/charhandle/isalpha_X/T.isalpha_X 03:16:19|TC Start, scenario ref 29-0
15|27 3.6-lite 1|TCM Start
400|27 1 1 03:16:19|IC Start
200|27 1 03:16:19|TP Start
220|27 1 0 03:16:19|PASS
410|27 1 1 03:16:19|IC End
80|27 0 03:16:20|TC End, scenario ref 29-0
10|28 /tset/ANSI.os/charhandle/iscntrl/T.iscntrl 03:16:20|TC Start, scenario ref 30-0
15|28 3.6-lite 2|TCM Start
400|28 1 1 03:16:20|IC Start
200|28 1 03:16:20|TP Start
220|28 1 0 03:16:20|PASS
410|28 1 1 03:16:20|IC End
400|28 2 1 03:16:20|IC Start
200|28 2 03:16:20|TP Start
220|28 2 0 03:16:20|PASS
410|28 2 1 03:16:20|IC End
80|28 0 03:16:21|TC End, scenario ref 30-0
10|29 /tset/ANSI.os/charhandle/iscntrl_X/T.iscntrl_X 03:16:21|TC Start, scenario ref 31-0
15|29 3.6-lite 1|TCM Start
400|29 1 1 03:16:21|IC Start
200|29 1 03:16:21|TP Start
220|29 1 0 03:16:21|PASS
410|29 1 1 03:16:21|IC End
80|29 0 03:16:22|TC End, scenario ref 31-0
10|30 /tset/ANSI.os/charhandle/isdigit/T.isdigit 03:16:22|TC Start, scenario ref 32-0
15|30 3.6-lite 1|TCM Start
400|30 1 1 03:16:22|IC Start
200|30 1 03:16:22|TP Start
220|30 1 0 03:16:22|PASS
410|30 1 1 03:16:22|IC End
80|30 0 03:16:23|TC End, scenario ref 32-0
10|31 /tset/ANSI.os/charhandle/isgraph/T.isgraph 03:16:23|TC Start, scenario ref 33-0
15|31 3.6-lite 2|TCM Start
400|31 1 1 03:16:23|IC Start
200|31 1 03:16:23|TP Start
220|31 1 0 03:16:23|PASS
410|31 1 1 03:16:23|IC End
400|31 2 1 03:16:23|IC Start
200|31 2 03:16:23|TP Start
220|31 2 0 03:16:23|PASS
410|31 2 1 03:16:23|IC End
80|31 0 03:16:24|TC End, scenario ref 33-0
10|32 /tset/ANSI.os/charhandle/isgraph_X/T.isgraph_X 03:16:24|TC Start, scenario ref 34-0
15|32 3.6-lite 1|TCM Start
400|32 1 1 03:16:24|IC Start
200|32 1 03:16:24|TP Start
220|32 1 0 03:16:24|PASS
410|32 1 1 03:16:24|IC End
80|32 0 03:16:25|TC End, scenario ref 34-0
10|33 /tset/ANSI.os/charhandle/islower/T.islower 03:16:25|TC Start, scenario ref 35-0
15|33 3.6-lite 2|TCM Start
400|33 1 1 03:16:25|IC Start
200|33 1 03:16:25|TP Start
220|33 1 0 03:16:25|PASS
410|33 1 1 03:16:25|IC End
400|33 2 1 03:16:25|IC Start
200|33 2 03:16:25|TP Start
220|33 2 0 03:16:25|PASS
410|33 2 1 03:16:25|IC End
80|33 0 03:16:26|TC End, scenario ref 35-0
10|34 /tset/ANSI.os/charhandle/islower_X/T.islower_X 03:16:26|TC Start, scenario ref 36-0
15|34 3.6-lite 1|TCM Start
400|34 1 1 03:16:26|IC Start
200|34 1 03:16:26|TP Start
220|34 1 0 03:16:26|PASS
410|34 1 1 03:16:26|IC End
80|34 0 03:16:27|TC End, scenario ref 36-0
10|35 /tset/ANSI.os/charhandle/isprint/T.isprint 03:16:27|TC Start, scenario ref 37-0
15|35 3.6-lite 2|TCM Start
400|35 1 1 03:16:27|IC Start
200|35 1 03:16:27|TP Start
220|35 1 0 03:16:27|PASS
410|35 1 1 03:16:27|IC End
400|35 2 1 03:16:27|IC Start
200|35 2 03:16:27|TP Start
220|35 2 0 03:16:27|PASS
410|35 2 1 03:16:27|IC End
80|35 0 03:16:28|TC End, scenario ref 37-0
10|36 /tset/ANSI.os/charhandle/isprint_X/T.isprint_X 03:16:28|TC Start, scenario ref 38-0
15|36 3.6-lite 1|TCM Start
400|36 1 1 03:16:28|IC Start
200|36 1 03:16:28|TP Start
220|36 1 0 03:16:28|PASS
410|36 1 1 03:16:28|IC End
80|36 0 03:16:29|TC End, scenario ref 38-0
10|37 /tset/ANSI.os/charhandle/ispunct/T.ispunct 03:16:29|TC Start, scenario ref 39-0
15|37 3.6-lite 2|TCM Start
400|37 1 1 03:16:29|IC Start
200|37 1 03:16:29|TP Start
220|37 1 0 03:16:29|PASS
410|37 1 1 03:16:29|IC End
400|37 2 1 03:16:29|IC Start
200|37 2 03:16:29|TP Start
220|37 2 0 03:16:29|PASS
410|37 2 1 03:16:29|IC End
80|37 0 03:16:30|TC End, scenario ref 39-0
10|38 /tset/ANSI.os/charhandle/ispunct_X/T.ispunct_X 03:16:30|TC Start, scenario ref 40-0
15|38 3.6-lite 1|TCM Start
400|38 1 1 03:16:30|IC Start
200|38 1 03:16:30|TP Start
220|38 1 0 03:16:30|PASS
410|38 1 1 03:16:30|IC End
80|38 0 03:16:31|TC End, scenario ref 40-0
10|39 /tset/ANSI.os/charhandle/isspace/T.isspace 03:16:31|TC Start, scenario ref 41-0
15|39 3.6-lite 2|TCM Start
400|39 1 1 03:16:31|IC Start
200|39 1 03:16:31|TP Start
220|39 1 0 03:16:31|PASS
410|39 1 1 03:16:31|IC End
400|39 2 1 03:16:31|IC Start
200|39 2 03:16:31|TP Start
220|39 2 0 03:16:31|PASS
410|39 2 1 03:16:31|IC End
80|39 0 03:16:32|TC End, scenario ref 41-0
10|40 /tset/ANSI.os/charhandle/isspace_X/T.isspace_X 03:16:32|TC Start, scenario ref 42-0
15|40 3.6-lite 1|TCM Start
400|40 1 1 03:16:32|IC Start
200|40 1 03:16:32|TP Start
220|40 1 0 03:16:32|PASS
410|40 1 1 03:16:32|IC End
80|40 0 03:16:33|TC End, scenario ref 42-0
10|41 /tset/ANSI.os/charhandle/isupper/T.isupper 03:16:33|TC Start, scenario ref 43-0
15|41 3.6-lite 2|TCM Start
400|41 1 1 03:16:33|IC Start
200|41 1 03:16:33|TP Start
220|41 1 0 03:16:33|PASS
410|41 1 1 03:16:33|IC End
400|41 2 1 03:16:33|IC Start
200|41 2 03:16:33|TP Start
220|41 2 0 03:16:33|PASS
410|41 2 1 03:16:33|IC End
80|41 0 03:16:34|TC End, scenario ref 43-0
10|42 /tset/ANSI.os/charhandle/isupper_X/T.isupper_X 03:16:34|TC Start, scenario ref 44-0
15|42 3.6-lite 1|TCM Start
400|42 1 1 03:16:34|IC Start
200|42 1 03:16:34|TP Start
220|42 1 0 03:16:34|PASS
410|42 1 1 03:16:34|IC End
80|42 0 03:16:35|TC End, scenario ref 44-0
10|43 /tset/ANSI.os/charhandle/isxdigit/T.isxdigit 03:16:35|TC Start, scenario ref 45-0
15|43 3.6-lite 1|TCM Start
400|43 1 1 03:16:35|IC Start
200|43 1 03:16:35|TP Start
220|43 1 0 03:16:35|PASS
410|43 1 1 03:16:35|IC End
80|43 0 03:16:36|TC End, scenario ref 45-0
10|44 /tset/ANSI.os/charhandle/tolower/T.tolower 03:16:36|TC Start, scenario ref 46-0
15|44 3.6-lite 3|TCM Start
400|44 1 1 03:16:36|IC Start
200|44 1 03:16:36|TP Start
220|44 1 0 03:16:36|PASS
410|44 1 1 03:16:36|IC End
400|44 2 1 03:16:36|IC Start
200|44 2 03:16:36|TP Start
220|44 2 0 03:16:36|PASS
410|44 2 1 03:16:36|IC End
400|44 3 1 03:16:36|IC Start
200|44 3 03:16:36|TP Start
220|44 3 0 03:16:36|PASS
410|44 3 1 03:16:36|IC End
80|44 0 03:16:37|TC End, scenario ref 46-0
10|45 /tset/ANSI.os/charhandle/tolower_X/T.tolower_X 03:16:37|TC Start, scenario ref 47-0
15|45 3.6-lite 1|TCM Start
400|45 1 1 03:16:37|IC Start
200|45 1 03:16:37|TP Start
220|45 1 0 03:16:37|PASS
410|45 1 1 03:16:37|IC End
80|45 0 03:16:38|TC End, scenario ref 47-0
10|46 /tset/ANSI.os/charhandle/toupper/T.toupper 03:16:38|TC Start, scenario ref 48-0
15|46 3.6-lite 3|TCM Start
400|46 1 1 03:16:38|IC Start
200|46 1 03:16:38|TP Start
220|46 1 0 03:16:38|PASS
410|46 1 1 03:16:38|IC End
400|46 2 1 03:16:38|IC Start
200|46 2 03:16:38|TP Start
220|46 2 0 03:16:38|PASS
410|46 2 1 03:16:38|IC End
400|46 3 1 03:16:38|IC Start
200|46 3 03:16:38|TP Start
220|46 3 0 03:16:38|PASS
410|46 3 1 03:16:38|IC End
80|46 0 03:16:39|TC End, scenario ref 48-0
10|47 /tset/ANSI.os/charhandle/toupper_X/T.toupper_X 03:16:39|TC Start, scenario ref 49-0
15|47 3.6-lite 1|TCM Start
400|47 1 1 03:16:39|IC Start
200|47 1 03:16:39|TP Start
220|47 1 0 03:16:39|PASS
410|47 1 1 03:16:39|IC End
80|47 0 03:16:40|TC End, scenario ref 49-0
10|48 /tset/ANSI.os/diagnostics/Massert/T.assert 03:16:40|TC Start, scenario ref 50-0
15|48 dummy 1|TCM Start
400|48 1 2 03:16:40|IC Start
200|48 1 03:16:40|TP Start
520|48 1 2227 1 1|No macros defined or no macro tests required
220|48 1 3 03:16:40|NOTINUSE
200|48 2 03:16:40|TP Start
520|48 2 2227 1 1|No macros defined or no macro tests required
220|48 2 3 03:16:40|NOTINUSE
410|48 1 2 03:16:40|IC End
80|48 0 03:16:41|TC End, scenario ref 50-0
10|49 /tset/ANSI.os/diagnostics/assert/T.assert 03:16:41|TC Start, scenario ref 51-0
15|49 3.6-lite 2|TCM Start
400|49 1 1 03:16:41|IC Start
200|49 1 03:16:41|TP Start
220|49 1 0 03:16:41|PASS
410|49 1 1 03:16:41|IC End
400|49 2 1 03:16:41|IC Start
200|49 2 03:16:41|TP Start
220|49 2 0 03:16:41|PASS
410|49 2 1 03:16:41|IC End
80|49 0 03:16:42|TC End, scenario ref 51-0
10|50 /tset/ANSI.os/genuts/Mabort/T.abort 03:16:42|TC Start, scenario ref 52-0
15|50 dummy 1|TCM Start
400|50 1 12 03:16:42|IC Start
200|50 1 03:16:42|TP Start
520|50 1 2233 1 1|No macros defined or no macro tests required
220|50 1 3 03:16:42|NOTINUSE
200|50 2 03:16:42|TP Start
520|50 2 2233 1 1|No macros defined or no macro tests required
220|50 2 3 03:16:42|NOTINUSE
200|50 3 03:16:42|TP Start
520|50 3 2233 1 1|No macros defined or no macro tests required
220|50 3 3 03:16:42|NOTINUSE
200|50 4 03:16:42|TP Start
520|50 4 2233 1 1|No macros defined or no macro tests required
220|50 4 3 03:16:42|NOTINUSE
200|50 5 03:16:42|TP Start
520|50 5 2233 1 1|No macros defined or no macro tests required
220|50 5 3 03:16:42|NOTINUSE
200|50 6 03:16:42|TP Start
520|50 6 2233 1 1|No macros defined or no macro tests required
220|50 6 3 03:16:42|NOTINUSE
200|50 7 03:16:42|TP Start
520|50 7 2233 1 1|No macros defined or no macro tests required
220|50 7 3 03:16:42|NOTINUSE
200|50 8 03:16:42|TP Start
520|50 8 2233 1 1|No macros defined or no macro tests required
220|50 8 3 03:16:42|NOTINUSE
200|50 9 03:16:42|TP Start
520|50 9 2233 1 1|No macros defined or no macro tests required
220|50 9 3 03:16:42|NOTINUSE
200|50 10 03:16:42|TP Start
520|50 10 2233 1 1|No macros defined or no macro tests required
220|50 10 3 03:16:42|NOTINUSE
200|50 11 03:16:42|TP Start
520|50 11 2233 1 1|No macros defined or no macro tests required
220|50 11 3 03:16:42|NOTINUSE
200|50 12 03:16:42|TP Start
520|50 12 2233 1 1|No macros defined or no macro tests required
220|50 12 3 03:16:42|NOTINUSE
410|50 1 12 03:16:42|IC End
80|50 0 03:16:43|TC End, scenario ref 52-0
10|51 /tset/ANSI.os/genuts/Mabs/T.abs 03:16:43|TC Start, scenario ref 53-0
15|51 dummy 1|TCM Start
400|51 1 1 03:16:43|IC Start
200|51 1 03:16:43|TP Start
520|51 1 2236 1 1|No macros defined or no macro tests required
220|51 1 3 03:16:43|NOTINUSE
410|51 1 1 03:16:43|IC End
80|51 0 03:16:44|TC End, scenario ref 53-0
10|52 /tset/ANSI.os/genuts/Matof/T.atof 03:16:44|TC Start, scenario ref 54-0
15|52 dummy 1|TCM Start
400|52 1 3 03:16:44|IC Start
200|52 1 03:16:44|TP Start
520|52 1 2239 1 1|No macros defined or no macro tests required
220|52 1 3 03:16:44|NOTINUSE
200|52 2 03:16:44|TP Start
520|52 2 2239 1 1|No macros defined or no macro tests required
220|52 2 3 03:16:44|NOTINUSE
200|52 3 03:16:44|TP Start
520|52 3 2239 1 1|No macros defined or no macro tests required
220|52 3 3 03:16:44|NOTINUSE
410|52 1 3 03:16:44|IC End
80|52 0 03:16:45|TC End, scenario ref 54-0
10|53 /tset/ANSI.os/genuts/Matoi/T.atoi 03:16:45|TC Start, scenario ref 55-0
15|53 dummy 1|TCM Start
400|53 1 2 03:16:45|IC Start
200|53 1 03:16:45|TP Start
520|53 1 2242 1 1|No macros defined or no macro tests required
220|53 1 3 03:16:45|NOTINUSE
200|53 2 03:16:45|TP Start
520|53 2 2242 1 1|No macros defined or no macro tests required
220|53 2 3 03:16:45|NOTINUSE
410|53 1 2 03:16:45|IC End
80|53 0 03:16:46|TC End, scenario ref 55-0
10|54 /tset/ANSI.os/genuts/Matol/T.atol 03:16:46|TC Start, scenario ref 56-0
15|54 dummy 1|TCM Start
400|54 1 2 03:16:46|IC Start
200|54 1 03:16:46|TP Start
520|54 1 2245 1 1|No macros defined or no macro tests required
220|54 1 3 03:16:46|NOTINUSE
200|54 2 03:16:46|TP Start
520|54 2 2245 1 1|No macros defined or no macro tests required
220|54 2 3 03:16:46|NOTINUSE
410|54 1 2 03:16:46|IC End
80|54 0 03:16:47|TC End, scenario ref 56-0
10|55 /tset/ANSI.os/genuts/Mbsearch/T.bsearch 03:16:47|TC Start, scenario ref 57-0
15|55 dummy 1|TCM Start
400|55 1 2 03:16:47|IC Start
200|55 1 03:16:47|TP Start
520|55 1 2248 1 1|No macros defined or no macro tests required
220|55 1 3 03:16:47|NOTINUSE
200|55 2 03:16:47|TP Start
520|55 2 2248 1 1|No macros defined or no macro tests required
220|55 2 3 03:16:47|NOTINUSE
410|55 1 2 03:16:47|IC End
80|55 0 03:16:48|TC End, scenario ref 57-0
10|56 /tset/ANSI.os/genuts/Mcalloc/T.calloc 03:16:48|TC Start, scenario ref 58-0
15|56 dummy 1|TCM Start
400|56 1 3 03:16:48|IC Start
200|56 1 03:16:48|TP Start
520|56 1 2251 1 1|No macros defined or no macro tests required
220|56 1 3 03:16:48|NOTINUSE
200|56 2 03:16:48|TP Start
520|56 2 2251 1 1|No macros defined or no macro tests required
220|56 2 3 03:16:48|NOTINUSE
200|56 3 03:16:48|TP Start
520|56 3 2251 1 1|No macros defined or no macro tests required
220|56 3 3 03:16:48|NOTINUSE
410|56 1 3 03:16:48|IC End
80|56 0 03:16:49|TC End, scenario ref 58-0
10|57 /tset/ANSI.os/genuts/Mexit/T.exit 03:16:49|TC Start, scenario ref 59-0
15|57 dummy 1|TCM Start
400|57 1 12 03:16:49|IC Start
200|57 1 03:16:49|TP Start
520|57 1 2254 1 1|No macros defined or no macro tests required
220|57 1 3 03:16:49|NOTINUSE
200|57 2 03:16:49|TP Start
520|57 2 2254 1 1|No macros defined or no macro tests required
220|57 2 3 03:16:49|NOTINUSE
200|57 3 03:16:49|TP Start
520|57 3 2254 1 1|No macros defined or no macro tests required
220|57 3 3 03:16:49|NOTINUSE
200|57 4 03:16:49|TP Start
520|57 4 2254 1 1|No macros defined or no macro tests required
220|57 4 3 03:16:49|NOTINUSE
200|57 5 03:16:49|TP Start
520|57 5 2254 1 1|No macros defined or no macro tests required
220|57 5 3 03:16:49|NOTINUSE
200|57 6 03:16:49|TP Start
520|57 6 2254 1 1|No macros defined or no macro tests required
220|57 6 3 03:16:49|NOTINUSE
200|57 7 03:16:49|TP Start
520|57 7 2254 1 1|No macros defined or no macro tests required
220|57 7 3 03:16:49|NOTINUSE
200|57 8 03:16:49|TP Start
520|57 8 2254 1 1|No macros defined or no macro tests required
220|57 8 3 03:16:49|NOTINUSE
200|57 9 03:16:49|TP Start
520|57 9 2254 1 1|No macros defined or no macro tests required
220|57 9 3 03:16:49|NOTINUSE
200|57 10 03:16:49|TP Start
520|57 10 2254 1 1|No macros defined or no macro tests required
220|57 10 3 03:16:49|NOTINUSE
200|57 11 03:16:49|TP Start
520|57 11 2254 1 1|No macros defined or no macro tests required
220|57 11 3 03:16:49|NOTINUSE
200|57 12 03:16:49|TP Start
520|57 12 2254 1 1|No macros defined or no macro tests required
220|57 12 3 03:16:49|NOTINUSE
410|57 1 12 03:16:49|IC End
80|57 0 03:16:50|TC End, scenario ref 59-0
10|58 /tset/ANSI.os/genuts/Mfree/T.free 03:16:50|TC Start, scenario ref 60-0
15|58 dummy 1|TCM Start
400|58 1 2 03:16:50|IC Start
200|58 1 03:16:50|TP Start
520|58 1 2257 1 1|No macros defined or no macro tests required
220|58 1 3 03:16:50|NOTINUSE
200|58 2 03:16:50|TP Start
520|58 2 2257 1 1|No macros defined or no macro tests required
220|58 2 3 03:16:50|NOTINUSE
410|58 1 2 03:16:50|IC End
80|58 0 03:16:51|TC End, scenario ref 60-0
10|59 /tset/ANSI.os/genuts/Mmalloc/T.malloc 03:16:51|TC Start, scenario ref 61-0
15|59 dummy 1|TCM Start
400|59 1 3 03:16:51|IC Start
200|59 1 03:16:51|TP Start
520|59 1 2260 1 1|No macros defined or no macro tests required
220|59 1 3 03:16:51|NOTINUSE
200|59 2 03:16:51|TP Start
520|59 2 2260 1 1|No macros defined or no macro tests required
220|59 2 3 03:16:51|NOTINUSE
200|59 3 03:16:51|TP Start
520|59 3 2260 1 1|No macros defined or no macro tests required
220|59 3 3 03:16:51|NOTINUSE
410|59 1 3 03:16:51|IC End
80|59 0 03:16:52|TC End, scenario ref 61-0
10|60 /tset/ANSI.os/genuts/Mqsort/T.qsort 03:16:52|TC Start, scenario ref 62-0
15|60 dummy 1|TCM Start
400|60 1 1 03:16:52|IC Start
200|60 1 03:16:52|TP Start
520|60 1 2263 1 1|No macros defined or no macro tests required
220|60 1 3 03:16:52|NOTINUSE
410|60 1 1 03:16:52|IC End
80|60 0 03:16:53|TC End, scenario ref 62-0
10|61 /tset/ANSI.os/genuts/Mrand/T.rand 03:16:53|TC Start, scenario ref 63-0
15|61 dummy 1|TCM Start
400|61 1 1 03:16:53|IC Start
200|61 1 03:16:53|TP Start
520|61 1 2266 1 1|No macros defined or no macro tests required
220|61 1 3 03:16:53|NOTINUSE
410|61 1 1 03:16:53|IC End
80|61 0 03:16:54|TC End, scenario ref 63-0
10|62 /tset/ANSI.os/genuts/Mrealloc/T.realloc 03:16:54|TC Start, scenario ref 64-0
15|62 dummy 1|TCM Start
400|62 1 6 03:16:54|IC Start
200|62 1 03:16:54|TP Start
520|62 1 2269 1 1|No macros defined or no macro tests required
220|62 1 3 03:16:54|NOTINUSE
200|62 2 03:16:54|TP Start
520|62 2 2269 1 1|No macros defined or no macro tests required
220|62 2 3 03:16:54|NOTINUSE
200|62 3 03:16:54|TP Start
520|62 3 2269 1 1|No macros defined or no macro tests required
220|62 3 3 03:16:54|NOTINUSE
200|62 4 03:16:54|TP Start
520|62 4 2269 1 1|No macros defined or no macro tests required
220|62 4 3 03:16:54|NOTINUSE
200|62 5 03:16:54|TP Start
520|62 5 2269 1 1|No macros defined or no macro tests required
220|62 5 3 03:16:54|NOTINUSE
200|62 6 03:16:54|TP Start
520|62 6 2269 1 1|No macros defined or no macro tests required
220|62 6 3 03:16:54|NOTINUSE
410|62 1 6 03:16:54|IC End
80|62 0 03:16:55|TC End, scenario ref 64-0
10|63 /tset/ANSI.os/genuts/Msrand/T.srand 03:16:55|TC Start, scenario ref 65-0
15|63 dummy 1|TCM Start
400|63 1 3 03:16:55|IC Start
200|63 1 03:16:55|TP Start
520|63 1 2272 1 1|No macros defined or no macro tests required
220|63 1 3 03:16:55|NOTINUSE
200|63 2 03:16:55|TP Start
520|63 2 2272 1 1|No macros defined or no macro tests required
220|63 2 3 03:16:55|NOTINUSE
200|63 3 03:16:55|TP Start
520|63 3 2272 1 1|No macros defined or no macro tests required
220|63 3 3 03:16:55|NOTINUSE
410|63 1 3 03:16:55|IC End
80|63 0 03:16:56|TC End, scenario ref 65-0
10|64 /tset/ANSI.os/genuts/Mstrtod_X/T.strtod_X 03:16:56|TC Start, scenario ref 66-0
15|64 dummy 1|TCM Start
400|64 1 7 03:16:56|IC Start
200|64 1 03:16:56|TP Start
520|64 1 2275 1 1|No macros defined or no macro tests required
220|64 1 3 03:16:56|NOTINUSE
200|64 2 03:16:56|TP Start
520|64 2 2275 1 1|No macros defined or no macro tests required
220|64 2 3 03:16:56|NOTINUSE
200|64 3 03:16:56|TP Start
520|64 3 2275 1 1|No macros defined or no macro tests required
220|64 3 3 03:16:56|NOTINUSE
200|64 4 03:16:56|TP Start
520|64 4 2275 1 1|No macros defined or no macro tests required
220|64 4 3 03:16:56|NOTINUSE
200|64 5 03:16:56|TP Start
520|64 5 2275 1 1|No macros defined or no macro tests required
220|64 5 3 03:16:56|NOTINUSE
200|64 6 03:16:56|TP Start
520|64 6 2275 1 1|No macros defined or no macro tests required
220|64 6 3 03:16:56|NOTINUSE
200|64 7 03:16:56|TP Start
520|64 7 2275 1 1|No macros defined or no macro tests required
220|64 7 3 03:16:56|NOTINUSE
410|64 1 7 03:16:56|IC End
80|64 0 03:16:57|TC End, scenario ref 66-0
10|65 /tset/ANSI.os/genuts/Mstrtol_X/T.strtol_X 03:16:57|TC Start, scenario ref 67-0
15|65 dummy 1|TCM Start
400|65 1 8 03:16:57|IC Start
200|65 1 03:16:57|TP Start
520|65 1 2278 1 1|No macros defined or no macro tests required
220|65 1 3 03:16:57|NOTINUSE
200|65 2 03:16:57|TP Start
520|65 2 2278 1 1|No macros defined or no macro tests required
220|65 2 3 03:16:57|NOTINUSE
200|65 3 03:16:57|TP Start
520|65 3 2278 1 1|No macros defined or no macro tests required
220|65 3 3 03:16:57|NOTINUSE
200|65 4 03:16:57|TP Start
520|65 4 2278 1 1|No macros defined or no macro tests required
220|65 4 3 03:16:57|NOTINUSE
200|65 5 03:16:57|TP Start
520|65 5 2278 1 1|No macros defined or no macro tests required
220|65 5 3 03:16:57|NOTINUSE
200|65 6 03:16:57|TP Start
520|65 6 2278 1 1|No macros defined or no macro tests required
220|65 6 3 03:16:57|NOTINUSE
200|65 7 03:16:57|TP Start
520|65 7 2278 1 1|No macros defined or no macro tests required
220|65 7 3 03:16:57|NOTINUSE
200|65 8 03:16:57|TP Start
520|65 8 2278 1 1|No macros defined or no macro tests required
220|65 8 3 03:16:57|NOTINUSE
410|65 1 8 03:16:57|IC End
80|65 0 03:16:58|TC End, scenario ref 67-0
10|66 /tset/ANSI.os/genuts/Msystem_X/T.system_X 03:16:58|TC Start, scenario ref 68-0
15|66 dummy 1|TCM Start
400|66 1 59 03:16:58|IC Start
200|66 1 03:16:58|TP Start
520|66 1 2281 1 1|No macros defined or no macro tests required
220|66 1 3 03:16:58|NOTINUSE
200|66 2 03:16:58|TP Start
520|66 2 2281 1 1|No macros defined or no macro tests required
220|66 2 3 03:16:58|NOTINUSE
200|66 3 03:16:58|TP Start
520|66 3 2281 1 1|No macros defined or no macro tests required
220|66 3 3 03:16:58|NOTINUSE
200|66 4 03:16:58|TP Start
520|66 4 2281 1 1|No macros defined or no macro tests required
220|66 4 3 03:16:58|NOTINUSE
200|66 5 03:16:58|TP Start
520|66 5 2281 1 1|No macros defined or no macro tests required
220|66 5 3 03:16:58|NOTINUSE
200|66 6 03:16:58|TP Start
520|66 6 2281 1 1|No macros defined or no macro tests required
220|66 6 3 03:16:58|NOTINUSE
200|66 7 03:16:58|TP Start
520|66 7 2281 1 1|No macros defined or no macro tests required
220|66 7 3 03:16:58|NOTINUSE
200|66 8 03:16:58|TP Start
520|66 8 2281 1 1|No macros defined or no macro tests required
220|66 8 3 03:16:58|NOTINUSE
200|66 9 03:16:58|TP Start
520|66 9 2281 1 1|No macros defined or no macro tests required
220|66 9 3 03:16:58|NOTINUSE
200|66 10 03:16:58|TP Start
520|66 10 2281 1 1|No macros defined or no macro tests required
220|66 10 3 03:16:58|NOTINUSE
200|66 11 03:16:58|TP Start
520|66 11 2281 1 1|No macros defined or no macro tests required
220|66 11 3 03:16:58|NOTINUSE
200|66 12 03:16:58|TP Start
520|66 12 2281 1 1|No macros defined or no macro tests required
220|66 12 3 03:16:58|NOTINUSE
200|66 13 03:16:58|TP Start
520|66 13 2281 1 1|No macros defined or no macro tests required
220|66 13 3 03:16:58|NOTINUSE
200|66 14 03:16:58|TP Start
520|66 14 2281 1 1|No macros defined or no macro tests required
220|66 14 3 03:16:58|NOTINUSE
200|66 15 03:16:58|TP Start
520|66 15 2281 1 1|No macros defined or no macro tests required
220|66 15 3 03:16:58|NOTINUSE
200|66 16 03:16:58|TP Start
520|66 16 2281 1 1|No macros defined or no macro tests required
220|66 16 3 03:16:58|NOTINUSE
200|66 17 03:16:58|TP Start
520|66 17 2281 1 1|No macros defined or no macro tests required
220|66 17 3 03:16:58|NOTINUSE
200|66 18 03:16:58|TP Start
520|66 18 2281 1 1|No macros defined or no macro tests required
220|66 18 3 03:16:58|NOTINUSE
200|66 19 03:16:58|TP Start
520|66 19 2281 1 1|No macros defined or no macro tests required
220|66 19 3 03:16:58|NOTINUSE
200|66 20 03:16:58|TP Start
520|66 20 2281 1 1|No macros defined or no macro tests required
220|66 20 3 03:16:58|NOTINUSE
200|66 21 03:16:58|TP Start
520|66 21 2281 1 1|No macros defined or no macro tests required
220|66 21 3 03:16:58|NOTINUSE
200|66 22 03:16:58|TP Start
520|66 22 2281 1 1|No macros defined or no macro tests required
220|66 22 3 03:16:58|NOTINUSE
200|66 23 03:16:58|TP Start
520|66 23 2281 1 1|No macros defined or no macro tests required
220|66 23 3 03:16:58|NOTINUSE
200|66 24 03:16:58|TP Start
520|66 24 2281 1 1|No macros defined or no macro tests required
220|66 24 3 03:16:58|NOTINUSE
200|66 25 03:16:58|TP Start
520|66 25 2281 1 1|No macros defined or no macro tests required
220|66 25 3 03:16:58|NOTINUSE
200|66 26 03:16:58|TP Start
520|66 26 2281 1 1|No macros defined or no macro tests required
220|66 26 3 03:16:58|NOTINUSE
200|66 27 03:16:58|TP Start
520|66 27 2281 1 1|No macros defined or no macro tests required
220|66 27 3 03:16:58|NOTINUSE
200|66 28 03:16:58|TP Start
520|66 28 2281 1 1|No macros defined or no macro tests required
220|66 28 3 03:16:58|NOTINUSE
200|66 29 03:16:58|TP Start
520|66 29 2281 1 1|No macros defined or no macro tests required
220|66 29 3 03:16:58|NOTINUSE
200|66 30 03:16:58|TP Start
520|66 30 2281 1 1|No macros defined or no macro tests required
220|66 30 3 03:16:58|NOTINUSE
200|66 31 03:16:58|TP Start
520|66 31 2281 1 1|No macros defined or no macro tests required
220|66 31 3 03:16:58|NOTINUSE
200|66 32 03:16:58|TP Start
520|66 32 2281 1 1|No macros defined or no macro tests required
220|66 32 3 03:16:58|NOTINUSE
200|66 33 03:16:58|TP Start
520|66 33 2281 1 1|No macros defined or no macro tests required
220|66 33 3 03:16:58|NOTINUSE
200|66 34 03:16:58|TP Start
520|66 34 2281 1 1|No macros defined or no macro tests required
220|66 34 3 03:16:58|NOTINUSE
200|66 35 03:16:58|TP Start
520|66 35 2281 1 1|No macros defined or no macro tests required
220|66 35 3 03:16:58|NOTINUSE
200|66 36 03:16:58|TP Start
520|66 36 2281 1 1|No macros defined or no macro tests required
220|66 36 3 03:16:58|NOTINUSE
200|66 37 03:16:58|TP Start
520|66 37 2281 1 1|No macros defined or no macro tests required
220|66 37 3 03:16:58|NOTINUSE
200|66 38 03:16:58|TP Start
520|66 38 2281 1 1|No macros defined or no macro tests required
220|66 38 3 03:16:58|NOTINUSE
200|66 39 03:16:58|TP Start
520|66 39 2281 1 1|No macros defined or no macro tests required
220|66 39 3 03:16:58|NOTINUSE
200|66 40 03:16:58|TP Start
520|66 40 2281 1 1|No macros defined or no macro tests required
220|66 40 3 03:16:58|NOTINUSE
200|66 41 03:16:58|TP Start
520|66 41 2281 1 1|No macros defined or no macro tests required
220|66 41 3 03:16:58|NOTINUSE
200|66 42 03:16:58|TP Start
520|66 42 2281 1 1|No macros defined or no macro tests required
220|66 42 3 03:16:58|NOTINUSE
200|66 43 03:16:58|TP Start
520|66 43 2281 1 1|No macros defined or no macro tests required
220|66 43 3 03:16:58|NOTINUSE
200|66 44 03:16:58|TP Start
520|66 44 2281 1 1|No macros defined or no macro tests required
220|66 44 3 03:16:58|NOTINUSE
200|66 45 03:16:58|TP Start
520|66 45 2281 1 1|No macros defined or no macro tests required
220|66 45 3 03:16:58|NOTINUSE
200|66 46 03:16:58|TP Start
520|66 46 2281 1 1|No macros defined or no macro tests required
220|66 46 3 03:16:58|NOTINUSE
200|66 47 03:16:58|TP Start
520|66 47 2281 1 1|No macros defined or no macro tests required
220|66 47 3 03:16:58|NOTINUSE
200|66 48 03:16:58|TP Start
520|66 48 2281 1 1|No macros defined or no macro tests required
220|66 48 3 03:16:58|NOTINUSE
200|66 49 03:16:58|TP Start
520|66 49 2281 1 1|No macros defined or no macro tests required
220|66 49 3 03:16:58|NOTINUSE
200|66 50 03:16:58|TP Start
520|66 50 2281 1 1|No macros defined or no macro tests required
220|66 50 3 03:16:58|NOTINUSE
200|66 51 03:16:58|TP Start
520|66 51 2281 1 1|No macros defined or no macro tests required
220|66 51 3 03:16:58|NOTINUSE
200|66 52 03:16:58|TP Start
520|66 52 2281 1 1|No macros defined or no macro tests required
220|66 52 3 03:16:58|NOTINUSE
200|66 53 03:16:58|TP Start
520|66 53 2281 1 1|No macros defined or no macro tests required
220|66 53 3 03:16:58|NOTINUSE
200|66 54 03:16:58|TP Start
520|66 54 2281 1 1|No macros defined or no macro tests required
220|66 54 3 03:16:58|NOTINUSE
200|66 55 03:16:58|TP Start
520|66 55 2281 1 1|No macros defined or no macro tests required
220|66 55 3 03:16:58|NOTINUSE
200|66 56 03:16:58|TP Start
520|66 56 2281 1 1|No macros defined or no macro tests required
220|66 56 3 03:16:58|NOTINUSE
200|66 57 03:16:58|TP Start
520|66 57 2281 1 1|No macros defined or no macro tests required
220|66 57 3 03:16:58|NOTINUSE
200|66 58 03:16:58|TP Start
520|66 58 2281 1 1|No macros defined or no macro tests required
220|66 58 3 03:16:58|NOTINUSE
200|66 59 03:16:58|TP Start
520|66 59 2281 1 1|No macros defined or no macro tests required
220|66 59 3 03:16:58|NOTINUSE
410|66 1 59 03:16:58|IC End
80|66 0 03:16:59|TC End, scenario ref 68-0
10|67 /tset/ANSI.os/genuts/abort/T.abort 03:16:59|TC Start, scenario ref 69-0
15|67 3.6-lite 12|TCM Start
400|67 1 1 03:16:59|IC Start
200|67 1 03:16:59|TP Start
220|67 1 0 03:16:59|PASS
410|67 1 1 03:16:59|IC End
400|67 2 1 03:16:59|IC Start
200|67 2 03:16:59|TP Start
220|67 2 0 03:18:39|PASS
410|67 2 1 03:18:39|IC End
400|67 3 1 03:18:39|IC Start
200|67 3 03:18:39|TP Start
220|67 3 0 03:19:27|PASS
410|67 3 1 03:19:27|IC End
400|67 4 1 03:19:27|IC Start
200|67 4 03:19:27|TP Start
220|67 4 0 03:21:55|PASS
410|67 4 1 03:21:55|IC End
400|67 5 1 03:21:55|IC Start
200|67 5 03:21:55|TP Start
220|67 5 0 03:24:23|PASS
410|67 5 1 03:24:23|IC End
400|67 6 1 03:24:23|IC Start
200|67 6 03:24:23|TP Start
220|67 6 0 03:25:11|PASS
410|67 6 1 03:25:11|IC End
400|67 7 1 03:25:11|IC Start
200|67 7 03:25:11|TP Start
220|67 7 0 03:27:07|PASS
410|67 7 1 03:27:07|IC End
400|67 8 1 03:27:07|IC Start
200|67 8 03:27:07|TP Start
220|67 8 0 03:27:55|PASS
410|67 8 1 03:27:55|IC End
400|67 9 1 03:27:55|IC Start
200|67 9 03:27:55|TP Start
220|67 9 0 03:28:43|PASS
410|67 9 1 03:28:43|IC End
400|67 10 1 03:28:43|IC Start
200|67 10 03:28:43|TP Start
220|67 10 0 03:29:31|PASS
410|67 10 1 03:29:31|IC End
400|67 11 1 03:29:31|IC Start
200|67 11 03:29:31|TP Start
220|67 11 0 03:32:23|PASS
410|67 11 1 03:32:23|IC End
400|67 12 1 03:32:23|IC Start
200|67 12 03:32:23|TP Start
220|67 12 3 03:32:23|NOTINUSE
410|67 12 1 03:32:23|IC End
80|67 0 03:32:26|TC End, scenario ref 69-0
10|68 /tset/ANSI.os/genuts/abs/T.abs 03:32:26|TC Start, scenario ref 70-0
15|68 3.6-lite 1|TCM Start
400|68 1 1 03:32:26|IC Start
200|68 1 03:32:26|TP Start
220|68 1 0 03:32:26|PASS
410|68 1 1 03:32:26|IC End
80|68 0 03:32:27|TC End, scenario ref 70-0
10|69 /tset/ANSI.os/genuts/atof/T.atof 03:32:27|TC Start, scenario ref 71-0
15|69 3.6-lite 3|TCM Start
400|69 1 1 03:32:27|IC Start
200|69 1 03:32:27|TP Start
220|69 1 0 03:32:27|PASS
410|69 1 1 03:32:27|IC End
400|69 2 1 03:32:27|IC Start
200|69 2 03:32:27|TP Start
220|69 2 0 03:32:27|PASS
410|69 2 1 03:32:27|IC End
400|69 3 1 03:32:27|IC Start
200|69 3 03:32:27|TP Start
220|69 3 0 03:32:27|PASS
410|69 3 1 03:32:27|IC End
80|69 0 03:32:28|TC End, scenario ref 71-0
10|70 /tset/ANSI.os/genuts/atoi/T.atoi 03:32:28|TC Start, scenario ref 72-0
15|70 3.6-lite 2|TCM Start
400|70 1 1 03:32:28|IC Start
200|70 1 03:32:28|TP Start
220|70 1 0 03:32:28|PASS
410|70 1 1 03:32:28|IC End
400|70 2 1 03:32:28|IC Start
200|70 2 03:32:28|TP Start
220|70 2 0 03:32:28|PASS
410|70 2 1 03:32:28|IC End
80|70 0 03:32:29|TC End, scenario ref 72-0
10|71 /tset/ANSI.os/genuts/atol/T.atol 03:32:29|TC Start, scenario ref 73-0
15|71 3.6-lite 2|TCM Start
400|71 1 1 03:32:29|IC Start
200|71 1 03:32:29|TP Start
220|71 1 0 03:32:29|PASS
410|71 1 1 03:32:29|IC End
400|71 2 1 03:32:29|IC Start
200|71 2 03:32:29|TP Start
220|71 2 0 03:32:29|PASS
410|71 2 1 03:32:29|IC End
80|71 0 03:32:30|TC End, scenario ref 73-0
10|72 /tset/ANSI.os/genuts/bsearch/T.bsearch 03:32:30|TC Start, scenario ref 74-0
15|72 3.6-lite 2|TCM Start
400|72 1 1 03:32:30|IC Start
200|72 1 03:32:30|TP Start
220|72 1 0 03:32:30|PASS
410|72 1 1 03:32:30|IC End
400|72 2 1 03:32:30|IC Start
200|72 2 03:32:30|TP Start
220|72 2 0 03:32:30|PASS
410|72 2 1 03:32:30|IC End
80|72 0 03:32:31|TC End, scenario ref 74-0
10|73 /tset/ANSI.os/genuts/calloc/T.calloc 03:32:31|TC Start, scenario ref 75-0
15|73 3.6-lite 3|TCM Start
400|73 1 1 03:32:31|IC Start
200|73 1 03:32:31|TP Start
220|73 1 0 03:32:31|PASS
410|73 1 1 03:32:31|IC End
400|73 2 1 03:32:31|IC Start
200|73 2 03:32:31|TP Start
220|73 2 0 03:32:31|PASS
410|73 2 1 03:32:31|IC End
400|73 3 1 03:32:31|IC Start
200|73 3 03:32:31|TP Start
220|73 3 0 03:32:31|PASS
410|73 3 1 03:32:31|IC End
80|73 0 03:32:32|TC End, scenario ref 75-0
10|74 /tset/ANSI.os/genuts/exit/T.exit 03:32:32|TC Start, scenario ref 76-0
15|74 3.6-lite 12|TCM Start
400|74 1 1 03:32:32|IC Start
200|74 1 03:32:32|TP Start
220|74 1 0 03:32:32|PASS
410|74 1 1 03:32:32|IC End
400|74 2 1 03:32:32|IC Start
200|74 2 03:32:32|TP Start
220|74 2 0 03:32:57|PASS
410|74 2 1 03:32:57|IC End
400|74 3 1 03:32:57|IC Start
200|74 3 03:32:57|TP Start
220|74 3 0 03:36:21|PASS
410|74 3 1 03:36:21|IC End
400|74 4 1 03:36:21|IC Start
200|74 4 03:36:21|TP Start
220|74 4 0 03:36:45|PASS
410|74 4 1 03:36:45|IC End
400|74 5 1 03:36:45|IC Start
200|74 5 03:36:45|TP Start
220|74 5 0 03:37:22|PASS
410|74 5 1 03:37:22|IC End
400|74 6 1 03:37:22|IC Start
200|74 6 03:37:22|TP Start
220|74 6 0 03:37:59|PASS
410|74 6 1 03:37:59|IC End
400|74 7 1 03:37:59|IC Start
200|74 7 03:37:59|TP Start
220|74 7 0 03:38:11|PASS
410|74 7 1 03:38:11|IC End
400|74 8 1 03:38:11|IC Start
200|74 8 03:38:11|TP Start
220|74 8 0 03:38:40|PASS
410|74 8 1 03:38:40|IC End
400|74 9 1 03:38:40|IC Start
200|74 9 03:38:40|TP Start
220|74 9 0 03:38:52|PASS
410|74 9 1 03:38:52|IC End
400|74 10 1 03:38:52|IC Start
200|74 10 03:38:52|TP Start
220|74 10 0 03:39:04|PASS
410|74 10 1 03:39:04|IC End
400|74 11 1 03:39:04|IC Start
200|74 11 03:39:04|TP Start
220|74 11 0 03:39:50|PASS
410|74 11 1 03:39:50|IC End
400|74 12 1 03:39:50|IC Start
200|74 12 03:39:50|TP Start
220|74 12 3 03:39:50|NOTINUSE
410|74 12 1 03:39:50|IC End
80|74 0 03:39:54|TC End, scenario ref 76-0
10|75 /tset/ANSI.os/genuts/free/T.free 03:39:54|TC Start, scenario ref 77-0
15|75 3.6-lite 2|TCM Start
400|75 1 1 03:39:54|IC Start
200|75 1 03:39:54|TP Start
220|75 1 0 03:39:54|PASS
410|75 1 1 03:39:54|IC End
400|75 2 1 03:39:54|IC Start
200|75 2 03:39:54|TP Start
220|75 2 0 03:39:54|PASS
410|75 2 1 03:39:54|IC End
80|75 0 03:39:55|TC End, scenario ref 77-0
10|76 /tset/ANSI.os/genuts/malloc/T.malloc 03:39:55|TC Start, scenario ref 78-0
15|76 3.6-lite 3|TCM Start
400|76 1 1 03:39:55|IC Start
200|76 1 03:39:55|TP Start
220|76 1 0 03:39:55|PASS
410|76 1 1 03:39:55|IC End
400|76 2 1 03:39:55|IC Start
200|76 2 03:39:55|TP Start
220|76 2 0 03:39:55|PASS
410|76 2 1 03:39:55|IC End
400|76 3 1 03:39:55|IC Start
200|76 3 03:39:55|TP Start
220|76 3 0 03:39:55|PASS
410|76 3 1 03:39:55|IC End
80|76 0 03:39:56|TC End, scenario ref 78-0
10|77 /tset/ANSI.os/genuts/qsort/T.qsort 03:39:56|TC Start, scenario ref 79-0
15|77 3.6-lite 1|TCM Start
400|77 1 1 03:39:56|IC Start
200|77 1 03:39:56|TP Start
220|77 1 0 03:39:56|PASS
410|77 1 1 03:39:56|IC End
80|77 0 03:39:57|TC End, scenario ref 79-0
10|78 /tset/ANSI.os/genuts/rand/T.rand 03:39:57|TC Start, scenario ref 80-0
15|78 3.6-lite 1|TCM Start
400|78 1 1 03:39:57|IC Start
200|78 1 03:39:57|TP Start
220|78 1 0 03:39:57|PASS
410|78 1 1 03:39:57|IC End
80|78 0 03:39:58|TC End, scenario ref 80-0
10|79 /tset/ANSI.os/genuts/realloc/T.realloc 03:39:58|TC Start, scenario ref 81-0
15|79 3.6-lite 6|TCM Start
400|79 1 1 03:39:58|IC Start
200|79 1 03:39:58|TP Start
220|79 1 0 03:39:58|PASS
410|79 1 1 03:39:58|IC End
400|79 2 1 03:39:58|IC Start
200|79 2 03:39:58|TP Start
220|79 2 0 03:39:58|PASS
410|79 2 1 03:39:58|IC End
400|79 3 1 03:39:58|IC Start
200|79 3 03:39:58|TP Start
220|79 3 0 03:39:58|PASS
410|79 3 1 03:39:58|IC End
400|79 4 1 03:39:58|IC Start
200|79 4 03:39:58|TP Start
220|79 4 0 03:39:58|PASS
410|79 4 1 03:39:58|IC End
400|79 5 1 03:39:58|IC Start
200|79 5 03:39:58|TP Start
220|79 5 0 03:39:58|PASS
410|79 5 1 03:39:58|IC End
400|79 6 1 03:39:58|IC Start
200|79 6 03:39:58|TP Start
220|79 6 0 03:39:58|PASS
410|79 6 1 03:39:58|IC End
80|79 0 03:39:59|TC End, scenario ref 81-0
10|80 /tset/ANSI.os/genuts/srand/T.srand 03:39:59|TC Start, scenario ref 82-0
15|80 3.6-lite 3|TCM Start
400|80 1 1 03:39:59|IC Start
200|80 1 03:39:59|TP Start
220|80 1 0 03:39:59|PASS
410|80 1 1 03:39:59|IC End
400|80 2 1 03:39:59|IC Start
200|80 2 03:39:59|TP Start
220|80 2 0 03:39:59|PASS
410|80 2 1 03:39:59|IC End
400|80 3 1 03:39:59|IC Start
200|80 3 03:39:59|TP Start
220|80 3 0 03:39:59|PASS
410|80 3 1 03:39:59|IC End
80|80 0 03:40:00|TC End, scenario ref 82-0
10|81 /tset/ANSI.os/genuts/strtod_X/T.strtod_X 03:40:00|TC Start, scenario ref 83-0
15|81 3.6-lite 7|TCM Start
400|81 1 1 03:40:00|IC Start
200|81 1 03:40:00|TP Start
220|81 1 0 03:40:00|PASS
410|81 1 1 03:40:00|IC End
400|81 2 1 03:40:00|IC Start
200|81 2 03:40:00|TP Start
220|81 2 0 03:40:00|PASS
410|81 2 1 03:40:00|IC End
400|81 3 1 03:40:00|IC Start
200|81 3 03:40:00|TP Start
220|81 3 0 03:40:00|PASS
410|81 3 1 03:40:00|IC End
400|81 4 1 03:40:00|IC Start
200|81 4 03:40:00|TP Start
220|81 4 0 03:40:00|PASS
410|81 4 1 03:40:00|IC End
400|81 5 1 03:40:00|IC Start
200|81 5 03:40:00|TP Start
220|81 5 0 03:40:00|PASS
410|81 5 1 03:40:00|IC End
400|81 6 1 03:40:00|IC Start
200|81 6 03:40:00|TP Start
220|81 6 0 03:40:00|PASS
410|81 6 1 03:40:00|IC End
400|81 7 1 03:40:00|IC Start
200|81 7 03:40:00|TP Start
220|81 7 0 03:40:00|PASS
410|81 7 1 03:40:00|IC End
80|81 0 03:40:01|TC End, scenario ref 83-0
10|82 /tset/ANSI.os/genuts/strtol_X/T.strtol_X 03:40:01|TC Start, scenario ref 84-0
15|82 3.6-lite 8|TCM Start
400|82 1 1 03:40:01|IC Start
200|82 1 03:40:01|TP Start
220|82 1 0 03:40:01|PASS
410|82 1 1 03:40:01|IC End
400|82 2 1 03:40:01|IC Start
200|82 2 03:40:01|TP Start
220|82 2 0 03:40:01|PASS
410|82 2 1 03:40:01|IC End
400|82 3 1 03:40:01|IC Start
200|82 3 03:40:01|TP Start
220|82 3 0 03:40:01|PASS
410|82 3 1 03:40:01|IC End
400|82 4 1 03:40:01|IC Start
200|82 4 03:40:01|TP Start
220|82 4 0 03:40:01|PASS
410|82 4 1 03:40:01|IC End
400|82 5 1 03:40:01|IC Start
200|82 5 03:40:01|TP Start
220|82 5 0 03:40:01|PASS
410|82 5 1 03:40:01|IC End
400|82 6 1 03:40:01|IC Start
200|82 6 03:40:01|TP Start
220|82 6 0 03:40:01|PASS
410|82 6 1 03:40:01|IC End
400|82 7 1 03:40:01|IC Start
200|82 7 03:40:01|TP Start
220|82 7 0 03:40:01|PASS
410|82 7 1 03:40:01|IC End
400|82 8 1 03:40:01|IC Start
200|82 8 03:40:01|TP Start
220|82 8 0 03:40:01|PASS
410|82 8 1 03:40:01|IC End
80|82 0 03:40:02|TC End, scenario ref 84-0
10|83 /tset/ANSI.os/genuts/system_X/T.system_X 03:40:02|TC Start, scenario ref 85-0
15|83 3.6-lite 59|TCM Start
400|83 1 1 03:40:02|IC Start
200|83 1 03:40:02|TP Start
220|83 1 0 03:40:02|PASS
410|83 1 1 03:40:02|IC End
400|83 2 1 03:40:02|IC Start
200|83 2 03:40:02|TP Start
220|83 2 0 03:40:02|PASS
410|83 2 1 03:40:02|IC End
400|83 3 1 03:40:02|IC Start
200|83 3 03:40:02|TP Start
220|83 3 0 03:40:02|PASS
410|83 3 1 03:40:02|IC End
400|83 4 1 03:40:02|IC Start
200|83 4 03:40:02|TP Start
220|83 4 0 03:40:02|PASS
410|83 4 1 03:40:02|IC End
400|83 5 1 03:40:02|IC Start
200|83 5 03:40:02|TP Start
220|83 5 0 03:40:02|PASS
410|83 5 1 03:40:02|IC End
400|83 6 1 03:40:02|IC Start
200|83 6 03:40:02|TP Start
220|83 6 0 03:40:02|PASS
410|83 6 1 03:40:02|IC End
400|83 7 1 03:40:02|IC Start
200|83 7 03:40:02|TP Start
220|83 7 0 03:40:02|PASS
410|83 7 1 03:40:02|IC End
400|83 8 1 03:40:02|IC Start
200|83 8 03:40:02|TP Start
220|83 8 0 03:40:02|PASS
410|83 8 1 03:40:02|IC End
400|83 9 1 03:40:02|IC Start
200|83 9 03:40:02|TP Start
220|83 9 0 03:40:02|PASS
410|83 9 1 03:40:02|IC End
400|83 10 1 03:40:02|IC Start
200|83 10 03:40:02|TP Start
220|83 10 0 03:40:02|PASS
410|83 10 1 03:40:02|IC End
400|83 11 1 03:40:02|IC Start
200|83 11 03:40:02|TP Start
220|83 11 0 03:40:02|PASS
410|83 11 1 03:40:02|IC End
400|83 12 1 03:40:02|IC Start
200|83 12 03:40:02|TP Start
220|83 12 0 03:40:02|PASS
410|83 12 1 03:40:02|IC End
400|83 13 1 03:40:02|IC Start
200|83 13 03:40:02|TP Start
220|83 13 0 03:40:03|PASS
410|83 13 1 03:40:03|IC End
400|83 14 1 03:40:03|IC Start
200|83 14 03:40:03|TP Start
220|83 14 0 03:40:03|PASS
410|83 14 1 03:40:03|IC End
400|83 15 1 03:40:03|IC Start
200|83 15 03:40:03|TP Start
220|83 15 0 03:40:03|PASS
410|83 15 1 03:40:03|IC End
400|83 16 1 03:40:03|IC Start
200|83 16 03:40:03|TP Start
220|83 16 0 03:40:03|PASS
410|83 16 1 03:40:03|IC End
400|83 17 1 03:40:03|IC Start
200|83 17 03:40:03|TP Start
220|83 17 0 03:40:03|PASS
410|83 17 1 03:40:03|IC End
400|83 18 1 03:40:03|IC Start
200|83 18 03:40:03|TP Start
220|83 18 0 03:40:03|PASS
410|83 18 1 03:40:03|IC End
400|83 19 1 03:40:03|IC Start
200|83 19 03:40:03|TP Start
220|83 19 0 03:40:03|PASS
410|83 19 1 03:40:03|IC End
400|83 20 1 03:40:03|IC Start
200|83 20 03:40:03|TP Start
220|83 20 0 03:40:28|PASS
410|83 20 1 03:40:28|IC End
400|83 21 1 03:40:28|IC Start
200|83 21 03:40:28|TP Start
220|83 21 0 03:40:28|PASS
410|83 21 1 03:40:28|IC End
400|83 22 1 03:40:28|IC Start
200|83 22 03:40:28|TP Start
220|83 22 0 03:40:28|PASS
410|83 22 1 03:40:28|IC End
400|83 23 1 03:40:28|IC Start
200|83 23 03:40:28|TP Start
220|83 23 0 03:40:28|PASS
410|83 23 1 03:40:28|IC End
400|83 24 1 03:40:28|IC Start
200|83 24 03:40:28|TP Start
220|83 24 0 03:41:18|PASS
410|83 24 1 03:41:18|IC End
400|83 25 1 03:41:18|IC Start
200|83 25 03:41:18|TP Start
220|83 25 0 03:42:08|PASS
410|83 25 1 03:42:08|IC End
400|83 26 1 03:42:08|IC Start
200|83 26 03:42:08|TP Start
220|83 26 0 03:42:58|PASS
410|83 26 1 03:42:58|IC End
400|83 27 1 03:42:58|IC Start
200|83 27 03:42:58|TP Start
220|83 27 0 03:42:58|PASS
410|83 27 1 03:42:58|IC End
400|83 28 1 03:42:58|IC Start
200|83 28 03:42:58|TP Start
220|83 28 0 03:42:58|PASS
410|83 28 1 03:42:58|IC End
400|83 29 1 03:42:58|IC Start
200|83 29 03:42:58|TP Start
220|83 29 0 03:42:58|PASS
410|83 29 1 03:42:58|IC End
400|83 30 1 03:42:58|IC Start
200|83 30 03:42:58|TP Start
220|83 30 0 03:42:58|PASS
410|83 30 1 03:42:58|IC End
400|83 31 1 03:42:58|IC Start
200|83 31 03:42:58|TP Start
220|83 31 0 03:42:58|PASS
410|83 31 1 03:42:58|IC End
400|83 32 1 03:42:58|IC Start
200|83 32 03:42:58|TP Start
220|83 32 0 03:42:58|PASS
410|83 32 1 03:42:58|IC End
400|83 33 1 03:42:58|IC Start
200|83 33 03:42:58|TP Start
220|83 33 0 03:42:58|PASS
410|83 33 1 03:42:58|IC End
400|83 34 1 03:42:58|IC Start
200|83 34 03:42:58|TP Start
220|83 34 0 03:42:58|PASS
410|83 34 1 03:42:58|IC End
400|83 35 1 03:42:58|IC Start
200|83 35 03:42:58|TP Start
220|83 35 0 03:42:58|PASS
410|83 35 1 03:42:58|IC End
400|83 36 1 03:42:58|IC Start
200|83 36 03:42:58|TP Start
220|83 36 0 03:42:58|PASS
410|83 36 1 03:42:58|IC End
400|83 37 1 03:42:58|IC Start
200|83 37 03:42:58|TP Start
220|83 37 0 03:42:58|PASS
410|83 37 1 03:42:58|IC End
400|83 38 1 03:42:58|IC Start
200|83 38 03:42:58|TP Start
220|83 38 0 03:42:58|PASS
410|83 38 1 03:42:58|IC End
400|83 39 1 03:42:58|IC Start
200|83 39 03:42:58|TP Start
220|83 39 0 03:42:58|PASS
410|83 39 1 03:42:58|IC End
400|83 40 1 03:42:58|IC Start
200|83 40 03:42:58|TP Start
220|83 40 0 03:42:58|PASS
410|83 40 1 03:42:58|IC End
400|83 41 1 03:42:58|IC Start
200|83 41 03:42:58|TP Start
220|83 41 0 03:42:58|PASS
410|83 41 1 03:42:58|IC End
400|83 42 1 03:42:58|IC Start
200|83 42 03:42:58|TP Start
220|83 42 0 03:42:58|PASS
410|83 42 1 03:42:58|IC End
400|83 43 1 03:42:58|IC Start
200|83 43 03:42:58|TP Start
220|83 43 0 03:42:58|PASS
410|83 43 1 03:42:58|IC End
400|83 44 1 03:42:58|IC Start
200|83 44 03:42:58|TP Start
220|83 44 0 03:42:58|PASS
410|83 44 1 03:42:58|IC End
400|83 45 1 03:42:58|IC Start
200|83 45 03:42:58|TP Start
220|83 45 0 03:42:58|PASS
410|83 45 1 03:42:58|IC End
400|83 46 1 03:42:58|IC Start
200|83 46 03:42:58|TP Start
220|83 46 0 03:42:58|PASS
410|83 46 1 03:42:58|IC End
400|83 47 1 03:42:58|IC Start
200|83 47 03:42:58|TP Start
220|83 47 0 03:42:58|PASS
410|83 47 1 03:42:58|IC End
400|83 48 1 03:42:58|IC Start
200|83 48 03:42:58|TP Start
220|83 48 0 03:42:58|PASS
410|83 48 1 03:42:58|IC End
400|83 49 1 03:42:58|IC Start
200|83 49 03:42:58|TP Start
220|83 49 0 03:42:58|PASS
410|83 49 1 03:42:58|IC End
400|83 50 1 03:42:58|IC Start
200|83 50 03:42:58|TP Start
220|83 50 0 03:43:08|PASS
410|83 50 1 03:43:08|IC End
400|83 51 1 03:43:08|IC Start
200|83 51 03:43:08|TP Start
220|83 51 0 03:43:18|PASS
410|83 51 1 03:43:18|IC End
400|83 52 1 03:43:18|IC Start
200|83 52 03:43:18|TP Start
220|83 52 0 03:43:33|PASS
410|83 52 1 03:43:33|IC End
400|83 53 1 03:43:33|IC Start
200|83 53 03:43:33|TP Start
220|83 53 0 03:44:08|PASS
410|83 53 1 03:44:08|IC End
400|83 54 1 03:44:08|IC Start
200|83 54 03:44:08|TP Start
220|83 54 0 03:44:08|PASS
410|83 54 1 03:44:08|IC End
400|83 55 1 03:44:08|IC Start
200|83 55 03:44:08|TP Start
220|83 55 3 03:44:08|NOTINUSE
410|83 55 1 03:44:08|IC End
400|83 56 1 03:44:08|IC Start
200|83 56 03:44:08|TP Start
220|83 56 0 03:44:08|PASS
410|83 56 1 03:44:08|IC End
400|83 57 1 03:44:08|IC Start
200|83 57 03:44:08|TP Start
220|83 57 0 03:44:08|PASS
410|83 57 1 03:44:08|IC End
400|83 58 1 03:44:08|IC Start
200|83 58 03:44:08|TP Start
520|83 58 00002703 1 1|sysconf(_SC_CHILD_MAX) returned > PCTS_CHILD_MAX
220|83 58 5 03:44:08|UNTESTED
410|83 58 1 03:44:08|IC End
400|83 59 1 03:44:08|IC Start
200|83 59 03:44:08|TP Start
220|83 59 0 03:44:18|PASS
410|83 59 1 03:44:18|IC End
80|83 0 03:44:19|TC End, scenario ref 85-0
10|84 /tset/ANSI.os/jump/Mlongjmp/T.longjmp 03:44:19|TC Start, scenario ref 86-0
15|84 dummy 1|TCM Start
400|84 1 2 03:44:19|IC Start
200|84 1 03:44:19|TP Start
520|84 1 2705 1 1|No macros defined or no macro tests required
220|84 1 3 03:44:19|NOTINUSE
200|84 2 03:44:19|TP Start
520|84 2 2705 1 1|No macros defined or no macro tests required
220|84 2 3 03:44:19|NOTINUSE
410|84 1 2 03:44:19|IC End
80|84 0 03:44:20|TC End, scenario ref 86-0
10|85 /tset/ANSI.os/jump/Msetjmp/T.setjmp 03:44:20|TC Start, scenario ref 87-0
15|85 dummy 1|TCM Start
400|85 1 2 03:44:20|IC Start
200|85 1 03:44:20|TP Start
520|85 1 2708 1 1|No macros defined or no macro tests required
220|85 1 3 03:44:20|NOTINUSE
200|85 2 03:44:20|TP Start
520|85 2 2708 1 1|No macros defined or no macro tests required
220|85 2 3 03:44:20|NOTINUSE
410|85 1 2 03:44:20|IC End
80|85 0 03:44:21|TC End, scenario ref 87-0
10|86 /tset/ANSI.os/jump/longjmp/T.longjmp 03:44:21|TC Start, scenario ref 88-0
15|86 3.6-lite 2|TCM Start
400|86 1 1 03:44:21|IC Start
200|86 1 03:44:21|TP Start
220|86 1 0 03:44:21|PASS
410|86 1 1 03:44:21|IC End
400|86 2 1 03:44:21|IC Start
200|86 2 03:44:21|TP Start
220|86 2 0 03:44:21|PASS
410|86 2 1 03:44:21|IC End
80|86 0 03:44:22|TC End, scenario ref 88-0
10|87 /tset/ANSI.os/jump/setjmp/T.setjmp 03:44:22|TC Start, scenario ref 89-0
15|87 3.6-lite 2|TCM Start
400|87 1 1 03:44:22|IC Start
200|87 1 03:44:22|TP Start
220|87 1 0 03:44:22|PASS
410|87 1 1 03:44:22|IC End
400|87 2 1 03:44:22|IC Start
200|87 2 03:44:22|TP Start
220|87 2 0 03:44:22|PASS
410|87 2 1 03:44:22|IC End
80|87 0 03:44:23|TC End, scenario ref 89-0
10|88 /tset/ANSI.os/locale/Msetlocale/T.setlocale 03:44:23|TC Start, scenario ref 90-0
15|88 dummy 1|TCM Start
400|88 1 18 03:44:23|IC Start
200|88 1 03:44:23|TP Start
520|88 1 2716 1 1|No macros defined or no macro tests required
220|88 1 3 03:44:23|NOTINUSE
200|88 2 03:44:23|TP Start
520|88 2 2716 1 1|No macros defined or no macro tests required
220|88 2 3 03:44:23|NOTINUSE
200|88 3 03:44:23|TP Start
520|88 3 2716 1 1|No macros defined or no macro tests required
220|88 3 3 03:44:23|NOTINUSE
200|88 4 03:44:23|TP Start
520|88 4 2716 1 1|No macros defined or no macro tests required
220|88 4 3 03:44:23|NOTINUSE
200|88 5 03:44:23|TP Start
520|88 5 2716 1 1|No macros defined or no macro tests required
220|88 5 3 03:44:23|NOTINUSE
200|88 6 03:44:23|TP Start
520|88 6 2716 1 1|No macros defined or no macro tests required
220|88 6 3 03:44:23|NOTINUSE
200|88 7 03:44:23|TP Start
520|88 7 2716 1 1|No macros defined or no macro tests required
220|88 7 3 03:44:23|NOTINUSE
200|88 8 03:44:23|TP Start
520|88 8 2716 1 1|No macros defined or no macro tests required
220|88 8 3 03:44:23|NOTINUSE
200|88 9 03:44:23|TP Start
520|88 9 2716 1 1|No macros defined or no macro tests required
220|88 9 3 03:44:23|NOTINUSE
200|88 10 03:44:23|TP Start
520|88 10 2716 1 1|No macros defined or no macro tests required
220|88 10 3 03:44:23|NOTINUSE
200|88 11 03:44:23|TP Start
520|88 11 2716 1 1|No macros defined or no macro tests required
220|88 11 3 03:44:23|NOTINUSE
200|88 12 03:44:23|TP Start
520|88 12 2716 1 1|No macros defined or no macro tests required
220|88 12 3 03:44:23|NOTINUSE
200|88 13 03:44:23|TP Start
520|88 13 2716 1 1|No macros defined or no macro tests required
220|88 13 3 03:44:23|NOTINUSE
200|88 14 03:44:23|TP Start
520|88 14 2716 1 1|No macros defined or no macro tests required
220|88 14 3 03:44:23|NOTINUSE
200|88 15 03:44:23|TP Start
520|88 15 2716 1 1|No macros defined or no macro tests required
220|88 15 3 03:44:23|NOTINUSE
200|88 16 03:44:23|TP Start
520|88 16 2716 1 1|No macros defined or no macro tests required
220|88 16 3 03:44:23|NOTINUSE
200|88 17 03:44:23|TP Start
520|88 17 2716 1 1|No macros defined or no macro tests required
220|88 17 3 03:44:23|NOTINUSE
200|88 18 03:44:23|TP Start
520|88 18 2716 1 1|No macros defined or no macro tests required
220|88 18 3 03:44:23|NOTINUSE
410|88 1 18 03:44:23|IC End
80|88 0 03:44:24|TC End, scenario ref 90-0
10|89 /tset/ANSI.os/locale/setlocale/T.setlocale 03:44:24|TC Start, scenario ref 91-0
15|89 3.6-lite 18|TCM Start
400|89 1 1 03:44:24|IC Start
200|89 1 03:44:24|TP Start
220|89 1 0 03:44:24|PASS
410|89 1 1 03:44:24|IC End
400|89 2 1 03:44:24|IC Start
200|89 2 03:44:24|TP Start
220|89 2 0 03:44:24|PASS
410|89 2 1 03:44:24|IC End
400|89 3 1 03:44:24|IC Start
200|89 3 03:44:24|TP Start
220|89 3 0 03:44:24|PASS
410|89 3 1 03:44:24|IC End
400|89 4 1 03:44:24|IC Start
200|89 4 03:44:24|TP Start
220|89 4 0 03:44:24|PASS
410|89 4 1 03:44:24|IC End
400|89 5 1 03:44:24|IC Start
200|89 5 03:44:24|TP Start
220|89 5 0 03:44:24|PASS
410|89 5 1 03:44:24|IC End
400|89 6 1 03:44:24|IC Start
200|89 6 03:44:24|TP Start
220|89 6 0 03:44:24|PASS
410|89 6 1 03:44:24|IC End
400|89 7 1 03:44:24|IC Start
200|89 7 03:44:24|TP Start
220|89 7 0 03:44:24|PASS
410|89 7 1 03:44:24|IC End
400|89 8 1 03:44:24|IC Start
200|89 8 03:44:24|TP Start
220|89 8 0 03:44:24|PASS
410|89 8 1 03:44:24|IC End
400|89 9 1 03:44:24|IC Start
200|89 9 03:44:24|TP Start
220|89 9 0 03:44:24|PASS
410|89 9 1 03:44:24|IC End
400|89 10 1 03:44:24|IC Start
200|89 10 03:44:24|TP Start
220|89 10 0 03:44:24|PASS
410|89 10 1 03:44:24|IC End
400|89 11 1 03:44:24|IC Start
200|89 11 03:44:24|TP Start
220|89 11 0 03:44:24|PASS
410|89 11 1 03:44:24|IC End
400|89 12 1 03:44:24|IC Start
200|89 12 03:44:24|TP Start
220|89 12 0 03:44:24|PASS
410|89 12 1 03:44:24|IC End
400|89 13 1 03:44:24|IC Start
200|89 13 03:44:24|TP Start
220|89 13 0 03:44:24|PASS
410|89 13 1 03:44:24|IC End
400|89 14 1 03:44:24|IC Start
200|89 14 03:44:24|TP Start
220|89 14 0 03:44:24|PASS
410|89 14 1 03:44:24|IC End
400|89 15 1 03:44:24|IC Start
200|89 15 03:44:24|TP Start
220|89 15 0 03:44:24|PASS
410|89 15 1 03:44:24|IC End
400|89 16 1 03:44:24|IC Start
200|89 16 03:44:24|TP Start
220|89 16 0 03:44:24|PASS
410|89 16 1 03:44:24|IC End
400|89 17 1 03:44:24|IC Start
200|89 17 03:44:24|TP Start
220|89 17 0 03:44:24|PASS
410|89 17 1 03:44:24|IC End
400|89 18 1 03:44:24|IC Start
200|89 18 03:44:24|TP Start
220|89 18 0 03:44:24|PASS
410|89 18 1 03:44:24|IC End
80|89 0 03:44:25|TC End, scenario ref 91-0
10|90 /tset/ANSI.os/maths/Macos/T.acos 03:44:25|TC Start, scenario ref 92-0
15|90 dummy 1|TCM Start
400|90 1 4 03:44:25|IC Start
200|90 1 03:44:25|TP Start
520|90 1 2739 1 1|No macros defined or no macro tests required
220|90 1 3 03:44:25|NOTINUSE
200|90 2 03:44:25|TP Start
520|90 2 2739 1 1|No macros defined or no macro tests required
220|90 2 3 03:44:25|NOTINUSE
200|90 3 03:44:25|TP Start
520|90 3 2739 1 1|No macros defined or no macro tests required
220|90 3 3 03:44:25|NOTINUSE
200|90 4 03:44:25|TP Start
520|90 4 2739 1 1|No macros defined or no macro tests required
220|90 4 3 03:44:25|NOTINUSE
410|90 1 4 03:44:25|IC End
80|90 0 03:44:26|TC End, scenario ref 92-0
10|91 /tset/ANSI.os/maths/Masin/T.asin 03:44:26|TC Start, scenario ref 93-0
15|91 dummy 1|TCM Start
400|91 1 4 03:44:26|IC Start
200|91 1 03:44:26|TP Start
520|91 1 2742 1 1|No macros defined or no macro tests required
220|91 1 3 03:44:26|NOTINUSE
200|91 2 03:44:26|TP Start
520|91 2 2742 1 1|No macros defined or no macro tests required
220|91 2 3 03:44:26|NOTINUSE
200|91 3 03:44:26|TP Start
520|91 3 2742 1 1|No macros defined or no macro tests required
220|91 3 3 03:44:26|NOTINUSE
200|91 4 03:44:26|TP Start
520|91 4 2742 1 1|No macros defined or no macro tests required
220|91 4 3 03:44:26|NOTINUSE
410|91 1 4 03:44:26|IC End
80|91 0 03:44:27|TC End, scenario ref 93-0
10|92 /tset/ANSI.os/maths/Matan/T.atan 03:44:27|TC Start, scenario ref 94-0
15|92 dummy 1|TCM Start
400|92 1 3 03:44:27|IC Start
200|92 1 03:44:27|TP Start
520|92 1 2745 1 1|No macros defined or no macro tests required
220|92 1 3 03:44:27|NOTINUSE
200|92 2 03:44:27|TP Start
520|92 2 2745 1 1|No macros defined or no macro tests required
220|92 2 3 03:44:27|NOTINUSE
200|92 3 03:44:27|TP Start
520|92 3 2745 1 1|No macros defined or no macro tests required
220|92 3 3 03:44:27|NOTINUSE
410|92 1 3 03:44:27|IC End
80|92 0 03:44:28|TC End, scenario ref 94-0
10|93 /tset/ANSI.os/maths/Matan2/T.atan2 03:44:28|TC Start, scenario ref 95-0
15|93 dummy 1|TCM Start
400|93 1 3 03:44:28|IC Start
200|93 1 03:44:28|TP Start
520|93 1 2748 1 1|No macros defined or no macro tests required
220|93 1 3 03:44:28|NOTINUSE
200|93 2 03:44:28|TP Start
520|93 2 2748 1 1|No macros defined or no macro tests required
220|93 2 3 03:44:28|NOTINUSE
200|93 3 03:44:28|TP Start
520|93 3 2748 1 1|No macros defined or no macro tests required
220|93 3 3 03:44:28|NOTINUSE
410|93 1 3 03:44:28|IC End
80|93 0 03:44:29|TC End, scenario ref 95-0
10|94 /tset/ANSI.os/maths/Mceil/T.ceil 03:44:29|TC Start, scenario ref 96-0
15|94 dummy 1|TCM Start
400|94 1 2 03:44:29|IC Start
200|94 1 03:44:29|TP Start
520|94 1 2751 1 1|No macros defined or no macro tests required
220|94 1 3 03:44:29|NOTINUSE
200|94 2 03:44:29|TP Start
520|94 2 2751 1 1|No macros defined or no macro tests required
220|94 2 3 03:44:29|NOTINUSE
410|94 1 2 03:44:29|IC End
80|94 0 03:44:30|TC End, scenario ref 96-0
10|95 /tset/ANSI.os/maths/Mcos/T.cos 03:44:30|TC Start, scenario ref 97-0
15|95 dummy 1|TCM Start
400|95 1 4 03:44:30|IC Start
200|95 1 03:44:30|TP Start
520|95 1 2754 1 1|No macros defined or no macro tests required
220|95 1 3 03:44:30|NOTINUSE
200|95 2 03:44:30|TP Start
520|95 2 2754 1 1|No macros defined or no macro tests required
220|95 2 3 03:44:30|NOTINUSE
200|95 3 03:44:30|TP Start
520|95 3 2754 1 1|No macros defined or no macro tests required
220|95 3 3 03:44:30|NOTINUSE
200|95 4 03:44:30|TP Start
520|95 4 2754 1 1|No macros defined or no macro tests required
220|95 4 3 03:44:30|NOTINUSE
410|95 1 4 03:44:30|IC End
80|95 0 03:44:31|TC End, scenario ref 97-0
10|96 /tset/ANSI.os/maths/Mcosh/T.cosh 03:44:31|TC Start, scenario ref 98-0
15|96 dummy 1|TCM Start
400|96 1 3 03:44:31|IC Start
200|96 1 03:44:31|TP Start
520|96 1 2757 1 1|No macros defined or no macro tests required
220|96 1 3 03:44:31|NOTINUSE
200|96 2 03:44:31|TP Start
520|96 2 2757 1 1|No macros defined or no macro tests required
220|96 2 3 03:44:31|NOTINUSE
200|96 3 03:44:31|TP Start
520|96 3 2757 1 1|No macros defined or no macro tests required
220|96 3 3 03:44:31|NOTINUSE
410|96 1 3 03:44:31|IC End
80|96 0 03:44:32|TC End, scenario ref 98-0
10|97 /tset/ANSI.os/maths/Mexp/T.exp 03:44:32|TC Start, scenario ref 99-0
15|97 dummy 1|TCM Start
400|97 1 4 03:44:32|IC Start
200|97 1 03:44:32|TP Start
520|97 1 2760 1 1|No macros defined or no macro tests required
220|97 1 3 03:44:32|NOTINUSE
200|97 2 03:44:32|TP Start
520|97 2 2760 1 1|No macros defined or no macro tests required
220|97 2 3 03:44:32|NOTINUSE
200|97 3 03:44:32|TP Start
520|97 3 2760 1 1|No macros defined or no macro tests required
220|97 3 3 03:44:32|NOTINUSE
200|97 4 03:44:32|TP Start
520|97 4 2760 1 1|No macros defined or no macro tests required
220|97 4 3 03:44:32|NOTINUSE
410|97 1 4 03:44:32|IC End
80|97 0 03:44:33|TC End, scenario ref 99-0
10|98 /tset/ANSI.os/maths/Mfabs/T.fabs 03:44:33|TC Start, scenario ref 100-0
15|98 dummy 1|TCM Start
400|98 1 2 03:44:33|IC Start
200|98 1 03:44:33|TP Start
520|98 1 2763 1 1|No macros defined or no macro tests required
220|98 1 3 03:44:33|NOTINUSE
200|98 2 03:44:33|TP Start
520|98 2 2763 1 1|No macros defined or no macro tests required
220|98 2 3 03:44:33|NOTINUSE
410|98 1 2 03:44:33|IC End
80|98 0 03:44:34|TC End, scenario ref 100-0
10|99 /tset/ANSI.os/maths/Mfloor/T.floor 03:44:34|TC Start, scenario ref 101-0
15|99 dummy 1|TCM Start
400|99 1 2 03:44:34|IC Start
200|99 1 03:44:34|TP Start
520|99 1 2766 1 1|No macros defined or no macro tests required
220|99 1 3 03:44:34|NOTINUSE
200|99 2 03:44:34|TP Start
520|99 2 2766 1 1|No macros defined or no macro tests required
220|99 2 3 03:44:34|NOTINUSE
410|99 1 2 03:44:34|IC End
80|99 0 03:44:35|TC End, scenario ref 101-0
10|100 /tset/ANSI.os/maths/Mfmod/T.fmod 03:44:35|TC Start, scenario ref 102-0
15|100 dummy 1|TCM Start
400|100 1 4 03:44:35|IC Start
200|100 1 03:44:35|TP Start
520|100 1 2769 1 1|No macros defined or no macro tests required
220|100 1 3 03:44:35|NOTINUSE
200|100 2 03:44:35|TP Start
520|100 2 2769 1 1|No macros defined or no macro tests required
220|100 2 3 03:44:35|NOTINUSE
200|100 3 03:44:35|TP Start
520|100 3 2769 1 1|No macros defined or no macro tests required
220|100 3 3 03:44:35|NOTINUSE
200|100 4 03:44:35|TP Start
520|100 4 2769 1 1|No macros defined or no macro tests required
220|100 4 3 03:44:35|NOTINUSE
410|100 1 4 03:44:35|IC End
80|100 0 03:44:36|TC End, scenario ref 102-0
10|101 /tset/ANSI.os/maths/Mfrexp/T.frexp 03:44:36|TC Start, scenario ref 103-0
15|101 dummy 1|TCM Start
400|101 1 4 03:44:36|IC Start
200|101 1 03:44:36|TP Start
520|101 1 2772 1 1|No macros defined or no macro tests required
220|101 1 3 03:44:36|NOTINUSE
200|101 2 03:44:36|TP Start
520|101 2 2772 1 1|No macros defined or no macro tests required
220|101 2 3 03:44:36|NOTINUSE
200|101 3 03:44:36|TP Start
520|101 3 2772 1 1|No macros defined or no macro tests required
220|101 3 3 03:44:36|NOTINUSE
200|101 4 03:44:36|TP Start
520|101 4 2772 1 1|No macros defined or no macro tests required
220|101 4 3 03:44:36|NOTINUSE
410|101 1 4 03:44:36|IC End
80|101 0 03:44:37|TC End, scenario ref 103-0
10|102 /tset/ANSI.os/maths/Mldexp/T.ldexp 03:44:37|TC Start, scenario ref 104-0
15|102 dummy 1|TCM Start
400|102 1 5 03:44:37|IC Start
200|102 1 03:44:37|TP Start
520|102 1 2775 1 1|No macros defined or no macro tests required
220|102 1 3 03:44:37|NOTINUSE
200|102 2 03:44:37|TP Start
520|102 2 2775 1 1|No macros defined or no macro tests required
220|102 2 3 03:44:37|NOTINUSE
200|102 3 03:44:37|TP Start
520|102 3 2775 1 1|No macros defined or no macro tests required
220|102 3 3 03:44:37|NOTINUSE
200|102 4 03:44:37|TP Start
520|102 4 2775 1 1|No macros defined or no macro tests required
220|102 4 3 03:44:37|NOTINUSE
200|102 5 03:44:37|TP Start
520|102 5 2775 1 1|No macros defined or no macro tests required
220|102 5 3 03:44:37|NOTINUSE
410|102 1 5 03:44:37|IC End
80|102 0 03:44:38|TC End, scenario ref 104-0
10|103 /tset/ANSI.os/maths/Mlog/T.log 03:44:38|TC Start, scenario ref 105-0
15|103 dummy 1|TCM Start
400|103 1 5 03:44:38|IC Start
200|103 1 03:44:38|TP Start
520|103 1 2778 1 1|No macros defined or no macro tests required
220|103 1 3 03:44:38|NOTINUSE
200|103 2 03:44:38|TP Start
520|103 2 2778 1 1|No macros defined or no macro tests required
220|103 2 3 03:44:38|NOTINUSE
200|103 3 03:44:38|TP Start
520|103 3 2778 1 1|No macros defined or no macro tests required
220|103 3 3 03:44:38|NOTINUSE
200|103 4 03:44:38|TP Start
520|103 4 2778 1 1|No macros defined or no macro tests required
220|103 4 3 03:44:38|NOTINUSE
200|103 5 03:44:38|TP Start
520|103 5 2778 1 1|No macros defined or no macro tests required
220|103 5 3 03:44:38|NOTINUSE
410|103 1 5 03:44:38|IC End
80|103 0 03:44:39|TC End, scenario ref 105-0
10|104 /tset/ANSI.os/maths/Mlog10/T.log10 03:44:39|TC Start, scenario ref 106-0
15|104 dummy 1|TCM Start
400|104 1 5 03:44:39|IC Start
200|104 1 03:44:39|TP Start
520|104 1 2781 1 1|No macros defined or no macro tests required
220|104 1 3 03:44:39|NOTINUSE
200|104 2 03:44:39|TP Start
520|104 2 2781 1 1|No macros defined or no macro tests required
220|104 2 3 03:44:39|NOTINUSE
200|104 3 03:44:39|TP Start
520|104 3 2781 1 1|No macros defined or no macro tests required
220|104 3 3 03:44:39|NOTINUSE
200|104 4 03:44:39|TP Start
520|104 4 2781 1 1|No macros defined or no macro tests required
220|104 4 3 03:44:39|NOTINUSE
200|104 5 03:44:39|TP Start
520|104 5 2781 1 1|No macros defined or no macro tests required
220|104 5 3 03:44:39|NOTINUSE
410|104 1 5 03:44:39|IC End
80|104 0 03:44:40|TC End, scenario ref 106-0
10|105 /tset/ANSI.os/maths/Mmodf/T.modf 03:44:40|TC Start, scenario ref 107-0
15|105 dummy 1|TCM Start
400|105 1 3 03:44:40|IC Start
200|105 1 03:44:40|TP Start
520|105 1 2784 1 1|No macros defined or no macro tests required
220|105 1 3 03:44:40|NOTINUSE
200|105 2 03:44:40|TP Start
520|105 2 2784 1 1|No macros defined or no macro tests required
220|105 2 3 03:44:40|NOTINUSE
200|105 3 03:44:40|TP Start
520|105 3 2784 1 1|No macros defined or no macro tests required
220|105 3 3 03:44:40|NOTINUSE
410|105 1 3 03:44:40|IC End
80|105 0 03:44:41|TC End, scenario ref 107-0
10|106 /tset/ANSI.os/maths/Mpow/T.pow 03:44:41|TC Start, scenario ref 108-0
15|106 dummy 1|TCM Start
400|106 1 8 03:44:41|IC Start
200|106 1 03:44:41|TP Start
520|106 1 2787 1 1|No macros defined or no macro tests required
220|106 1 3 03:44:41|NOTINUSE
200|106 2 03:44:41|TP Start
520|106 2 2787 1 1|No macros defined or no macro tests required
220|106 2 3 03:44:41|NOTINUSE
200|106 3 03:44:41|TP Start
520|106 3 2787 1 1|No macros defined or no macro tests required
220|106 3 3 03:44:41|NOTINUSE
200|106 4 03:44:41|TP Start
520|106 4 2787 1 1|No macros defined or no macro tests required
220|106 4 3 03:44:41|NOTINUSE
200|106 5 03:44:41|TP Start
520|106 5 2787 1 1|No macros defined or no macro tests required
220|106 5 3 03:44:41|NOTINUSE
200|106 6 03:44:41|TP Start
520|106 6 2787 1 1|No macros defined or no macro tests required
220|106 6 3 03:44:41|NOTINUSE
200|106 7 03:44:41|TP Start
520|106 7 2787 1 1|No macros defined or no macro tests required
220|106 7 3 03:44:41|NOTINUSE
200|106 8 03:44:41|TP Start
520|106 8 2787 1 1|No macros defined or no macro tests required
220|106 8 3 03:44:41|NOTINUSE
410|106 1 8 03:44:41|IC End
80|106 0 03:44:42|TC End, scenario ref 108-0
10|107 /tset/ANSI.os/maths/Msin/T.sin 03:44:42|TC Start, scenario ref 109-0
15|107 dummy 1|TCM Start
400|107 1 4 03:44:42|IC Start
200|107 1 03:44:42|TP Start
520|107 1 2790 1 1|No macros defined or no macro tests required
220|107 1 3 03:44:42|NOTINUSE
200|107 2 03:44:42|TP Start
520|107 2 2790 1 1|No macros defined or no macro tests required
220|107 2 3 03:44:42|NOTINUSE
200|107 3 03:44:42|TP Start
520|107 3 2790 1 1|No macros defined or no macro tests required
220|107 3 3 03:44:42|NOTINUSE
200|107 4 03:44:42|TP Start
520|107 4 2790 1 1|No macros defined or no macro tests required
220|107 4 3 03:44:42|NOTINUSE
410|107 1 4 03:44:42|IC End
80|107 0 03:44:43|TC End, scenario ref 109-0
10|108 /tset/ANSI.os/maths/Msinh/T.sinh 03:44:43|TC Start, scenario ref 110-0
15|108 dummy 1|TCM Start
400|108 1 3 03:44:43|IC Start
200|108 1 03:44:43|TP Start
520|108 1 2793 1 1|No macros defined or no macro tests required
220|108 1 3 03:44:43|NOTINUSE
200|108 2 03:44:43|TP Start
520|108 2 2793 1 1|No macros defined or no macro tests required
220|108 2 3 03:44:43|NOTINUSE
200|108 3 03:44:43|TP Start
520|108 3 2793 1 1|No macros defined or no macro tests required
220|108 3 3 03:44:43|NOTINUSE
410|108 1 3 03:44:43|IC End
80|108 0 03:44:44|TC End, scenario ref 110-0
10|109 /tset/ANSI.os/maths/Msqrt/T.sqrt 03:44:44|TC Start, scenario ref 111-0
15|109 dummy 1|TCM Start
400|109 1 3 03:44:44|IC Start
200|109 1 03:44:44|TP Start
520|109 1 2796 1 1|No macros defined or no macro tests required
220|109 1 3 03:44:44|NOTINUSE
200|109 2 03:44:44|TP Start
520|109 2 2796 1 1|No macros defined or no macro tests required
220|109 2 3 03:44:44|NOTINUSE
200|109 3 03:44:44|TP Start
520|109 3 2796 1 1|No macros defined or no macro tests required
220|109 3 3 03:44:44|NOTINUSE
410|109 1 3 03:44:44|IC End
80|109 0 03:44:45|TC End, scenario ref 111-0
10|110 /tset/ANSI.os/maths/Mtan/T.tan 03:44:45|TC Start, scenario ref 112-0
15|110 dummy 1|TCM Start
400|110 1 4 03:44:45|IC Start
200|110 1 03:44:45|TP Start
520|110 1 2799 1 1|No macros defined or no macro tests required
220|110 1 3 03:44:45|NOTINUSE
200|110 2 03:44:45|TP Start
520|110 2 2799 1 1|No macros defined or no macro tests required
220|110 2 3 03:44:45|NOTINUSE
200|110 3 03:44:45|TP Start
520|110 3 2799 1 1|No macros defined or no macro tests required
220|110 3 3 03:44:45|NOTINUSE
200|110 4 03:44:45|TP Start
520|110 4 2799 1 1|No macros defined or no macro tests required
220|110 4 3 03:44:45|NOTINUSE
410|110 1 4 03:44:45|IC End
80|110 0 03:44:46|TC End, scenario ref 112-0
10|111 /tset/ANSI.os/maths/Mtanh/T.tanh 03:44:46|TC Start, scenario ref 113-0
15|111 dummy 1|TCM Start
400|111 1 2 03:44:46|IC Start
200|111 1 03:44:46|TP Start
520|111 1 2802 1 1|No macros defined or no macro tests required
220|111 1 3 03:44:46|NOTINUSE
200|111 2 03:44:46|TP Start
520|111 2 2802 1 1|No macros defined or no macro tests required
220|111 2 3 03:44:46|NOTINUSE
410|111 1 2 03:44:46|IC End
80|111 0 03:44:47|TC End, scenario ref 113-0
10|112 /tset/ANSI.os/maths/acos/T.acos 03:44:47|TC Start, scenario ref 114-0
15|112 3.6-lite 4|TCM Start
400|112 1 1 03:44:47|IC Start
200|112 1 03:44:47|TP Start
220|112 1 0 03:44:47|PASS
410|112 1 1 03:44:47|IC End
400|112 2 1 03:44:47|IC Start
200|112 2 03:44:47|TP Start
220|112 2 0 03:44:47|PASS
410|112 2 1 03:44:47|IC End
400|112 3 1 03:44:47|IC Start
200|112 3 03:44:47|TP Start
220|112 3 0 03:44:47|PASS
410|112 3 1 03:44:47|IC End
400|112 4 1 03:44:47|IC Start
200|112 4 03:44:47|TP Start
220|112 4 0 03:44:47|PASS
410|112 4 1 03:44:47|IC End
80|112 0 03:44:48|TC End, scenario ref 114-0
10|113 /tset/ANSI.os/maths/asin/T.asin 03:44:48|TC Start, scenario ref 115-0
15|113 3.6-lite 4|TCM Start
400|113 1 1 03:44:48|IC Start
200|113 1 03:44:48|TP Start
220|113 1 0 03:44:48|PASS
410|113 1 1 03:44:48|IC End
400|113 2 1 03:44:48|IC Start
200|113 2 03:44:48|TP Start
220|113 2 0 03:44:48|PASS
410|113 2 1 03:44:48|IC End
400|113 3 1 03:44:48|IC Start
200|113 3 03:44:48|TP Start
220|113 3 0 03:44:48|PASS
410|113 3 1 03:44:48|IC End
400|113 4 1 03:44:48|IC Start
200|113 4 03:44:48|TP Start
220|113 4 0 03:44:48|PASS
410|113 4 1 03:44:48|IC End
80|113 0 03:44:49|TC End, scenario ref 115-0
10|114 /tset/ANSI.os/maths/atan/T.atan 03:44:49|TC Start, scenario ref 116-0
15|114 3.6-lite 3|TCM Start
400|114 1 1 03:44:49|IC Start
200|114 1 03:44:49|TP Start
220|114 1 0 03:44:49|PASS
410|114 1 1 03:44:49|IC End
400|114 2 1 03:44:49|IC Start
200|114 2 03:44:49|TP Start
220|114 2 0 03:44:49|PASS
410|114 2 1 03:44:49|IC End
400|114 3 1 03:44:49|IC Start
200|114 3 03:44:49|TP Start
220|114 3 0 03:44:49|PASS
410|114 3 1 03:44:49|IC End
80|114 0 03:44:50|TC End, scenario ref 116-0
10|115 /tset/ANSI.os/maths/atan2/T.atan2 03:44:50|TC Start, scenario ref 117-0
15|115 3.6-lite 3|TCM Start
400|115 1 1 03:44:50|IC Start
200|115 1 03:44:50|TP Start
220|115 1 0 03:44:50|PASS
410|115 1 1 03:44:50|IC End
400|115 2 1 03:44:50|IC Start
200|115 2 03:44:50|TP Start
220|115 2 0 03:44:50|PASS
410|115 2 1 03:44:50|IC End
400|115 3 1 03:44:50|IC Start
200|115 3 03:44:50|TP Start
220|115 3 0 03:44:50|PASS
410|115 3 1 03:44:50|IC End
80|115 0 03:44:51|TC End, scenario ref 117-0
10|116 /tset/ANSI.os/maths/ceil/T.ceil 03:44:51|TC Start, scenario ref 118-0
15|116 3.6-lite 2|TCM Start
400|116 1 1 03:44:51|IC Start
200|116 1 03:44:51|TP Start
220|116 1 0 03:44:51|PASS
410|116 1 1 03:44:51|IC End
400|116 2 1 03:44:51|IC Start
200|116 2 03:44:51|TP Start
220|116 2 0 03:44:51|PASS
410|116 2 1 03:44:51|IC End
80|116 0 03:44:52|TC End, scenario ref 118-0
10|117 /tset/ANSI.os/maths/cos/T.cos 03:44:52|TC Start, scenario ref 119-0
15|117 3.6-lite 4|TCM Start
400|117 1 1 03:44:52|IC Start
200|117 1 03:44:52|TP Start
220|117 1 0 03:44:52|PASS
410|117 1 1 03:44:52|IC End
400|117 2 1 03:44:52|IC Start
200|117 2 03:44:52|TP Start
220|117 2 0 03:44:52|PASS
410|117 2 1 03:44:52|IC End
400|117 3 1 03:44:52|IC Start
200|117 3 03:44:52|TP Start
220|117 3 3 03:44:52|NOTINUSE
410|117 3 1 03:44:52|IC End
400|117 4 1 03:44:52|IC Start
200|117 4 03:44:52|TP Start
220|117 4 0 03:44:52|PASS
410|117 4 1 03:44:52|IC End
80|117 0 03:44:53|TC End, scenario ref 119-0
10|118 /tset/ANSI.os/maths/cosh/T.cosh 03:44:53|TC Start, scenario ref 120-0
15|118 3.6-lite 3|TCM Start
400|118 1 1 03:44:53|IC Start
200|118 1 03:44:53|TP Start
220|118 1 0 03:44:53|PASS
410|118 1 1 03:44:53|IC End
400|118 2 1 03:44:53|IC Start
200|118 2 03:44:53|TP Start
220|118 2 0 03:44:53|PASS
410|118 2 1 03:44:53|IC End
400|118 3 1 03:44:53|IC Start
200|118 3 03:44:53|TP Start
220|118 3 0 03:44:53|PASS
410|118 3 1 03:44:53|IC End
80|118 0 03:44:54|TC End, scenario ref 120-0
10|119 /tset/ANSI.os/maths/exp/T.exp 03:44:54|TC Start, scenario ref 121-0
15|119 3.6-lite 4|TCM Start
400|119 1 1 03:44:54|IC Start
200|119 1 03:44:54|TP Start
220|119 1 0 03:44:54|PASS
410|119 1 1 03:44:54|IC End
400|119 2 1 03:44:54|IC Start
200|119 2 03:44:54|TP Start
220|119 2 0 03:44:54|PASS
410|119 2 1 03:44:54|IC End
400|119 3 1 03:44:54|IC Start
200|119 3 03:44:54|TP Start
220|119 3 0 03:44:54|PASS
410|119 3 1 03:44:54|IC End
400|119 4 1 03:44:54|IC Start
200|119 4 03:44:54|TP Start
220|119 4 0 03:44:54|PASS
410|119 4 1 03:44:54|IC End
80|119 0 03:44:55|TC End, scenario ref 121-0
10|120 /tset/ANSI.os/maths/fabs/T.fabs 03:44:55|TC Start, scenario ref 122-0
15|120 3.6-lite 2|TCM Start
400|120 1 1 03:44:55|IC Start
200|120 1 03:44:55|TP Start
220|120 1 0 03:44:55|PASS
410|120 1 1 03:44:55|IC End
400|120 2 1 03:44:55|IC Start
200|120 2 03:44:55|TP Start
220|120 2 0 03:44:55|PASS
410|120 2 1 03:44:55|IC End
80|120 0 03:44:56|TC End, scenario ref 122-0
10|121 /tset/ANSI.os/maths/floor/T.floor 03:44:56|TC Start, scenario ref 123-0
15|121 3.6-lite 2|TCM Start
400|121 1 1 03:44:56|IC Start
200|121 1 03:44:56|TP Start
220|121 1 0 03:44:56|PASS
410|121 1 1 03:44:56|IC End
400|121 2 1 03:44:56|IC Start
200|121 2 03:44:56|TP Start
220|121 2 0 03:44:56|PASS
410|121 2 1 03:44:56|IC End
80|121 0 03:44:57|TC End, scenario ref 123-0
10|122 /tset/ANSI.os/maths/fmod/T.fmod 03:44:57|TC Start, scenario ref 124-0
15|122 3.6-lite 4|TCM Start
400|122 1 1 03:44:57|IC Start
200|122 1 03:44:57|TP Start
220|122 1 0 03:44:57|PASS
410|122 1 1 03:44:57|IC End
400|122 2 1 03:44:57|IC Start
200|122 2 03:44:57|TP Start
220|122 2 0 03:44:57|PASS
410|122 2 1 03:44:57|IC End
400|122 3 1 03:44:57|IC Start
200|122 3 03:44:57|TP Start
220|122 3 0 03:44:57|PASS
410|122 3 1 03:44:57|IC End
400|122 4 1 03:44:57|IC Start
200|122 4 03:44:57|TP Start
220|122 4 0 03:44:57|PASS
410|122 4 1 03:44:57|IC End
80|122 0 03:44:58|TC End, scenario ref 124-0
10|123 /tset/ANSI.os/maths/frexp/T.frexp 03:44:58|TC Start, scenario ref 125-0
15|123 3.6-lite 4|TCM Start
400|123 1 1 03:44:58|IC Start
200|123 1 03:44:58|TP Start
220|123 1 0 03:44:58|PASS
410|123 1 1 03:44:58|IC End
400|123 2 1 03:44:58|IC Start
200|123 2 03:44:58|TP Start
220|123 2 0 03:44:58|PASS
410|123 2 1 03:44:58|IC End
400|123 3 1 03:44:58|IC Start
200|123 3 03:44:58|TP Start
220|123 3 0 03:44:58|PASS
410|123 3 1 03:44:58|IC End
400|123 4 1 03:44:58|IC Start
200|123 4 03:44:58|TP Start
220|123 4 0 03:44:58|PASS
410|123 4 1 03:44:58|IC End
80|123 0 03:44:59|TC End, scenario ref 125-0
10|124 /tset/ANSI.os/maths/ldexp/T.ldexp 03:44:59|TC Start, scenario ref 126-0
15|124 3.6-lite 5|TCM Start
400|124 1 1 03:44:59|IC Start
200|124 1 03:44:59|TP Start
220|124 1 0 03:44:59|PASS
410|124 1 1 03:44:59|IC End
400|124 2 1 03:44:59|IC Start
200|124 2 03:44:59|TP Start
220|124 2 0 03:44:59|PASS
410|124 2 1 03:44:59|IC End
400|124 3 1 03:44:59|IC Start
200|124 3 03:44:59|TP Start
220|124 3 0 03:44:59|PASS
410|124 3 1 03:44:59|IC End
400|124 4 1 03:44:59|IC Start
200|124 4 03:44:59|TP Start
220|124 4 0 03:44:59|PASS
410|124 4 1 03:44:59|IC End
400|124 5 1 03:44:59|IC Start
200|124 5 03:44:59|TP Start
220|124 5 0 03:44:59|PASS
410|124 5 1 03:44:59|IC End
80|124 0 03:45:00|TC End, scenario ref 126-0
10|125 /tset/ANSI.os/maths/log/T.log 03:45:00|TC Start, scenario ref 127-0
15|125 3.6-lite 5|TCM Start
400|125 1 1 03:45:00|IC Start
200|125 1 03:45:00|TP Start
220|125 1 0 03:45:00|PASS
410|125 1 1 03:45:00|IC End
400|125 2 1 03:45:00|IC Start
200|125 2 03:45:00|TP Start
220|125 2 0 03:45:00|PASS
410|125 2 1 03:45:00|IC End
400|125 3 1 03:45:00|IC Start
200|125 3 03:45:00|TP Start
220|125 3 0 03:45:00|PASS
410|125 3 1 03:45:00|IC End
400|125 4 1 03:45:00|IC Start
200|125 4 03:45:00|TP Start
220|125 4 0 03:45:00|PASS
410|125 4 1 03:45:00|IC End
400|125 5 1 03:45:00|IC Start
200|125 5 03:45:00|TP Start
220|125 5 0 03:45:00|PASS
410|125 5 1 03:45:00|IC End
80|125 0 03:45:01|TC End, scenario ref 127-0
10|126 /tset/ANSI.os/maths/log10/T.log10 03:45:01|TC Start, scenario ref 128-0
15|126 3.6-lite 5|TCM Start
400|126 1 1 03:45:01|IC Start
200|126 1 03:45:01|TP Start
220|126 1 0 03:45:01|PASS
410|126 1 1 03:45:01|IC End
400|126 2 1 03:45:01|IC Start
200|126 2 03:45:01|TP Start
220|126 2 0 03:45:01|PASS
410|126 2 1 03:45:01|IC End
400|126 3 1 03:45:01|IC Start
200|126 3 03:45:01|TP Start
220|126 3 0 03:45:01|PASS
410|126 3 1 03:45:01|IC End
400|126 4 1 03:45:01|IC Start
200|126 4 03:45:01|TP Start
220|126 4 0 03:45:01|PASS
410|126 4 1 03:45:01|IC End
400|126 5 1 03:45:01|IC Start
200|126 5 03:45:01|TP Start
220|126 5 0 03:45:01|PASS
410|126 5 1 03:45:01|IC End
80|126 0 03:45:02|TC End, scenario ref 128-0
10|127 /tset/ANSI.os/maths/modf/T.modf 03:45:02|TC Start, scenario ref 129-0
15|127 3.6-lite 3|TCM Start
400|127 1 1 03:45:02|IC Start
200|127 1 03:45:02|TP Start
220|127 1 0 03:45:02|PASS
410|127 1 1 03:45:02|IC End
400|127 2 1 03:45:02|IC Start
200|127 2 03:45:02|TP Start
220|127 2 0 03:45:02|PASS
410|127 2 1 03:45:02|IC End
400|127 3 1 03:45:02|IC Start
200|127 3 03:45:02|TP Start
220|127 3 0 03:45:02|PASS
410|127 3 1 03:45:02|IC End
80|127 0 03:45:03|TC End, scenario ref 129-0
10|128 /tset/ANSI.os/maths/pow/T.pow 03:45:03|TC Start, scenario ref 130-0
15|128 3.6-lite 8|TCM Start
400|128 1 1 03:45:03|IC Start
200|128 1 03:45:03|TP Start
220|128 1 0 03:45:03|PASS
410|128 1 1 03:45:03|IC End
400|128 2 1 03:45:03|IC Start
200|128 2 03:45:03|TP Start
220|128 2 0 03:45:03|PASS
410|128 2 1 03:45:03|IC End
400|128 3 1 03:45:03|IC Start
200|128 3 03:45:03|TP Start
220|128 3 0 03:45:03|PASS
410|128 3 1 03:45:03|IC End
400|128 4 1 03:45:03|IC Start
200|128 4 03:45:03|TP Start
520|128 4 00002882 1 1|pow(0.0, -1.0) gave
520|128 4 00002882 1 2|RETURN VALUES: expected: -inf, observed: inf
520|128 4 00002882 1 3|    Bit Representation: expected value: \000\000\000\000\000\000\360\377
520|128 4 00002882 1 4|    Bit Representation: observed value: \000\000\000\000\000\000\360\177
220|128 4 101 03:45:03|WARNING
410|128 4 1 03:45:03|IC End
400|128 5 1 03:45:03|IC Start
200|128 5 03:45:03|TP Start
220|128 5 0 03:45:03|PASS
410|128 5 1 03:45:03|IC End
400|128 6 1 03:45:03|IC Start
200|128 6 03:45:03|TP Start
220|128 6 0 03:45:03|PASS
410|128 6 1 03:45:03|IC End
400|128 7 1 03:45:03|IC Start
200|128 7 03:45:03|TP Start
220|128 7 0 03:45:03|PASS
410|128 7 1 03:45:03|IC End
400|128 8 1 03:45:03|IC Start
200|128 8 03:45:03|TP Start
520|128 8 00002886 1 1|INFO:Part of this test case is not run in LSB_TEST mode
520|128 8 00002886 1 2|INFO:since glibc implements a future direction for
520|128 8 00002886 1 3|INFO:pow(NaN,(double)1.0) that matches XSH6
220|128 8 0 03:45:03|PASS
410|128 8 1 03:45:03|IC End
80|128 0 03:45:04|TC End, scenario ref 130-0
10|129 /tset/ANSI.os/maths/sin/T.sin 03:45:04|TC Start, scenario ref 131-0
15|129 3.6-lite 4|TCM Start
400|129 1 1 03:45:04|IC Start
200|129 1 03:45:04|TP Start
220|129 1 0 03:45:04|PASS
410|129 1 1 03:45:04|IC End
400|129 2 1 03:45:04|IC Start
200|129 2 03:45:04|TP Start
220|129 2 0 03:45:04|PASS
410|129 2 1 03:45:04|IC End
400|129 3 1 03:45:04|IC Start
200|129 3 03:45:04|TP Start
220|129 3 3 03:45:04|NOTINUSE
410|129 3 1 03:45:04|IC End
400|129 4 1 03:45:04|IC Start
200|129 4 03:45:04|TP Start
220|129 4 0 03:45:04|PASS
410|129 4 1 03:45:04|IC End
80|129 0 03:45:05|TC End, scenario ref 131-0
10|130 /tset/ANSI.os/maths/sinh/T.sinh 03:45:05|TC Start, scenario ref 132-0
15|130 3.6-lite 3|TCM Start
400|130 1 1 03:45:05|IC Start
200|130 1 03:45:05|TP Start
220|130 1 0 03:45:05|PASS
410|130 1 1 03:45:05|IC End
400|130 2 1 03:45:05|IC Start
200|130 2 03:45:05|TP Start
220|130 2 0 03:45:05|PASS
410|130 2 1 03:45:05|IC End
400|130 3 1 03:45:05|IC Start
200|130 3 03:45:05|TP Start
220|130 3 0 03:45:05|PASS
410|130 3 1 03:45:05|IC End
80|130 0 03:45:06|TC End, scenario ref 132-0
10|131 /tset/ANSI.os/maths/sqrt/T.sqrt 03:45:06|TC Start, scenario ref 133-0
15|131 3.6-lite 3|TCM Start
400|131 1 1 03:45:06|IC Start
200|131 1 03:45:06|TP Start
220|131 1 0 03:45:06|PASS
410|131 1 1 03:45:06|IC End
400|131 2 1 03:45:06|IC Start
200|131 2 03:45:06|TP Start
220|131 2 0 03:45:06|PASS
410|131 2 1 03:45:06|IC End
400|131 3 1 03:45:06|IC Start
200|131 3 03:45:06|TP Start
220|131 3 0 03:45:06|PASS
410|131 3 1 03:45:06|IC End
80|131 0 03:45:07|TC End, scenario ref 133-0
10|132 /tset/ANSI.os/maths/tan/T.tan 03:45:07|TC Start, scenario ref 134-0
15|132 3.6-lite 4|TCM Start
400|132 1 1 03:45:07|IC Start
200|132 1 03:45:07|TP Start
220|132 1 0 03:45:07|PASS
410|132 1 1 03:45:07|IC End
400|132 2 1 03:45:07|IC Start
200|132 2 03:45:07|TP Start
220|132 2 0 03:45:07|PASS
410|132 2 1 03:45:07|IC End
400|132 3 1 03:45:07|IC Start
200|132 3 03:45:07|TP Start
220|132 3 3 03:45:07|NOTINUSE
410|132 3 1 03:45:07|IC End
400|132 4 1 03:45:07|IC Start
200|132 4 03:45:07|TP Start
220|132 4 0 03:45:07|PASS
410|132 4 1 03:45:07|IC End
80|132 0 03:45:08|TC End, scenario ref 134-0
10|133 /tset/ANSI.os/maths/tanh/T.tanh 03:45:08|TC Start, scenario ref 135-0
15|133 3.6-lite 2|TCM Start
400|133 1 1 03:45:08|IC Start
200|133 1 03:45:08|TP Start
220|133 1 0 03:45:08|PASS
410|133 1 1 03:45:08|IC End
400|133 2 1 03:45:08|IC Start
200|133 2 03:45:08|TP Start
220|133 2 0 03:45:08|PASS
410|133 2 1 03:45:08|IC End
80|133 0 03:45:09|TC End, scenario ref 135-0
10|134 /tset/ANSI.os/signal/Msignal_X/T.signal_X 03:45:09|TC Start, scenario ref 136-0
15|134 dummy 1|TCM Start
400|134 1 9 03:45:09|IC Start
200|134 1 03:45:09|TP Start
520|134 1 2906 1 1|No macros defined or no macro tests required
220|134 1 3 03:45:09|NOTINUSE
200|134 2 03:45:09|TP Start
520|134 2 2906 1 1|No macros defined or no macro tests required
220|134 2 3 03:45:09|NOTINUSE
200|134 3 03:45:09|TP Start
520|134 3 2906 1 1|No macros defined or no macro tests required
220|134 3 3 03:45:09|NOTINUSE
200|134 4 03:45:09|TP Start
520|134 4 2906 1 1|No macros defined or no macro tests required
220|134 4 3 03:45:09|NOTINUSE
200|134 5 03:45:09|TP Start
520|134 5 2906 1 1|No macros defined or no macro tests required
220|134 5 3 03:45:09|NOTINUSE
200|134 6 03:45:09|TP Start
520|134 6 2906 1 1|No macros defined or no macro tests required
220|134 6 3 03:45:09|NOTINUSE
200|134 7 03:45:09|TP Start
520|134 7 2906 1 1|No macros defined or no macro tests required
220|134 7 3 03:45:09|NOTINUSE
200|134 8 03:45:09|TP Start
520|134 8 2906 1 1|No macros defined or no macro tests required
220|134 8 3 03:45:09|NOTINUSE
200|134 9 03:45:09|TP Start
520|134 9 2906 1 1|No macros defined or no macro tests required
220|134 9 3 03:45:09|NOTINUSE
410|134 1 9 03:45:09|IC End
80|134 0 03:45:10|TC End, scenario ref 136-0
10|135 /tset/ANSI.os/signal/signal_X/T.signal_X 03:45:10|TC Start, scenario ref 137-0
15|135 3.6-lite 9|TCM Start
400|135 1 1 03:45:10|IC Start
200|135 1 03:45:10|TP Start
220|135 1 0 03:45:10|PASS
410|135 1 1 03:45:10|IC End
400|135 2 1 03:45:10|IC Start
200|135 2 03:45:10|TP Start
220|135 2 0 03:47:58|PASS
410|135 2 1 03:47:58|IC End
400|135 3 1 03:47:58|IC Start
200|135 3 03:47:58|TP Start
220|135 3 0 03:47:58|PASS
410|135 3 1 03:47:58|IC End
400|135 4 1 03:47:58|IC Start
200|135 4 03:47:58|TP Start
220|135 4 0 03:48:19|PASS
410|135 4 1 03:48:19|IC End
400|135 5 1 03:48:19|IC Start
200|135 5 03:48:19|TP Start
220|135 5 0 03:48:40|PASS
410|135 5 1 03:48:40|IC End
400|135 6 1 03:48:40|IC Start
200|135 6 03:48:40|TP Start
220|135 6 0 03:48:59|PASS
410|135 6 1 03:48:59|IC End
400|135 7 1 03:48:59|IC Start
200|135 7 03:48:59|TP Start
220|135 7 0 03:50:23|PASS
410|135 7 1 03:50:23|IC End
400|135 8 1 03:50:23|IC Start
200|135 8 03:50:23|TP Start
220|135 8 0 03:50:43|PASS
410|135 8 1 03:50:43|IC End
400|135 9 1 03:50:43|IC Start
200|135 9 03:50:43|TP Start
220|135 9 0 03:50:43|PASS
410|135 9 1 03:50:43|IC End
80|135 0 03:50:47|TC End, scenario ref 137-0
10|136 /tset/ANSI.os/streamio/Mclearerr/T.clearerr 03:50:47|TC Start, scenario ref 138-0
15|136 dummy 1|TCM Start
400|136 1 1 03:50:47|IC Start
200|136 1 03:50:47|TP Start
520|136 1 3117 1 1|No macros defined or no macro tests required
220|136 1 3 03:50:47|NOTINUSE
410|136 1 1 03:50:47|IC End
80|136 0 03:50:48|TC End, scenario ref 138-0
10|137 /tset/ANSI.os/streamio/Mfclose/T.fclose 03:50:48|TC Start, scenario ref 139-0
15|137 dummy 1|TCM Start
400|137 1 21 03:50:48|IC Start
200|137 1 03:50:48|TP Start
520|137 1 3120 1 1|No macros defined or no macro tests required
220|137 1 3 03:50:48|NOTINUSE
200|137 2 03:50:48|TP Start
520|137 2 3120 1 1|No macros defined or no macro tests required
220|137 2 3 03:50:48|NOTINUSE
200|137 3 03:50:48|TP Start
520|137 3 3120 1 1|No macros defined or no macro tests required
220|137 3 3 03:50:48|NOTINUSE
200|137 4 03:50:48|TP Start
520|137 4 3120 1 1|No macros defined or no macro tests required
220|137 4 3 03:50:48|NOTINUSE
200|137 5 03:50:48|TP Start
520|137 5 3120 1 1|No macros defined or no macro tests required
220|137 5 3 03:50:48|NOTINUSE
200|137 6 03:50:48|TP Start
520|137 6 3120 1 1|No macros defined or no macro tests required
220|137 6 3 03:50:48|NOTINUSE
200|137 7 03:50:48|TP Start
520|137 7 3120 1 1|No macros defined or no macro tests required
220|137 7 3 03:50:48|NOTINUSE
200|137 8 03:50:48|TP Start
520|137 8 3120 1 1|No macros defined or no macro tests required
220|137 8 3 03:50:48|NOTINUSE
200|137 9 03:50:48|TP Start
520|137 9 3120 1 1|No macros defined or no macro tests required
220|137 9 3 03:50:48|NOTINUSE
200|137 10 03:50:48|TP Start
520|137 10 3120 1 1|No macros defined or no macro tests required
220|137 10 3 03:50:48|NOTINUSE
200|137 11 03:50:48|TP Start
520|137 11 3120 1 1|No macros defined or no macro tests required
220|137 11 3 03:50:48|NOTINUSE
200|137 12 03:50:48|TP Start
520|137 12 3120 1 1|No macros defined or no macro tests required
220|137 12 3 03:50:48|NOTINUSE
200|137 13 03:50:48|TP Start
520|137 13 3120 1 1|No macros defined or no macro tests required
220|137 13 3 03:50:48|NOTINUSE
200|137 14 03:50:48|TP Start
520|137 14 3120 1 1|No macros defined or no macro tests required
220|137 14 3 03:50:48|NOTINUSE
200|137 15 03:50:48|TP Start
520|137 15 3120 1 1|No macros defined or no macro tests required
220|137 15 3 03:50:48|NOTINUSE
200|137 16 03:50:48|TP Start
520|137 16 3120 1 1|No macros defined or no macro tests required
220|137 16 3 03:50:48|NOTINUSE
200|137 17 03:50:48|TP Start
520|137 17 3120 1 1|No macros defined or no macro tests required
220|137 17 3 03:50:48|NOTINUSE
200|137 18 03:50:48|TP Start
520|137 18 3120 1 1|No macros defined or no macro tests required
220|137 18 3 03:50:48|NOTINUSE
200|137 19 03:50:48|TP Start
520|137 19 3120 1 1|No macros defined or no macro tests required
220|137 19 3 03:50:48|NOTINUSE
200|137 20 03:50:48|TP Start
520|137 20 3120 1 1|No macros defined or no macro tests required
220|137 20 3 03:50:48|NOTINUSE
200|137 21 03:50:48|TP Start
520|137 21 3120 1 1|No macros defined or no macro tests required
220|137 21 3 03:50:48|NOTINUSE
410|137 1 21 03:50:48|IC End
80|137 0 03:50:49|TC End, scenario ref 139-0
10|138 /tset/ANSI.os/streamio/Mfeof/T.feof 03:50:49|TC Start, scenario ref 140-0
15|138 dummy 1|TCM Start
400|138 1 2 03:50:50|IC Start
200|138 1 03:50:50|TP Start
520|138 1 3123 1 1|No macros defined or no macro tests required
220|138 1 3 03:50:50|NOTINUSE
200|138 2 03:50:50|TP Start
520|138 2 3123 1 1|No macros defined or no macro tests required
220|138 2 3 03:50:50|NOTINUSE
410|138 1 2 03:50:50|IC End
80|138 0 03:50:50|TC End, scenario ref 140-0
10|139 /tset/ANSI.os/streamio/Mferror/T.ferror 03:50:50|TC Start, scenario ref 141-0
15|139 dummy 1|TCM Start
400|139 1 2 03:50:51|IC Start
200|139 1 03:50:51|TP Start
520|139 1 3126 1 1|No macros defined or no macro tests required
220|139 1 3 03:50:51|NOTINUSE
200|139 2 03:50:51|TP Start
520|139 2 3126 1 1|No macros defined or no macro tests required
220|139 2 3 03:50:51|NOTINUSE
410|139 1 2 03:50:51|IC End
80|139 0 03:50:51|TC End, scenario ref 141-0
10|140 /tset/ANSI.os/streamio/Mfflush/T.fflush 03:50:51|TC Start, scenario ref 142-0
15|140 dummy 1|TCM Start
400|140 1 15 03:50:52|IC Start
200|140 1 03:50:52|TP Start
520|140 1 3129 1 1|No macros defined or no macro tests required
220|140 1 3 03:50:52|NOTINUSE
200|140 2 03:50:52|TP Start
520|140 2 3129 1 1|No macros defined or no macro tests required
220|140 2 3 03:50:52|NOTINUSE
200|140 3 03:50:52|TP Start
520|140 3 3129 1 1|No macros defined or no macro tests required
220|140 3 3 03:50:52|NOTINUSE
200|140 4 03:50:52|TP Start
520|140 4 3129 1 1|No macros defined or no macro tests required
220|140 4 3 03:50:52|NOTINUSE
200|140 5 03:50:52|TP Start
520|140 5 3129 1 1|No macros defined or no macro tests required
220|140 5 3 03:50:52|NOTINUSE
200|140 6 03:50:52|TP Start
520|140 6 3129 1 1|No macros defined or no macro tests required
220|140 6 3 03:50:52|NOTINUSE
200|140 7 03:50:52|TP Start
520|140 7 3129 1 1|No macros defined or no macro tests required
220|140 7 3 03:50:52|NOTINUSE
200|140 8 03:50:52|TP Start
520|140 8 3129 1 1|No macros defined or no macro tests required
220|140 8 3 03:50:52|NOTINUSE
200|140 9 03:50:52|TP Start
520|140 9 3129 1 1|No macros defined or no macro tests required
220|140 9 3 03:50:52|NOTINUSE
200|140 10 03:50:52|TP Start
520|140 10 3129 1 1|No macros defined or no macro tests required
220|140 10 3 03:50:52|NOTINUSE
200|140 11 03:50:52|TP Start
520|140 11 3129 1 1|No macros defined or no macro tests required
220|140 11 3 03:50:52|NOTINUSE
200|140 12 03:50:52|TP Start
520|140 12 3129 1 1|No macros defined or no macro tests required
220|140 12 3 03:50:52|NOTINUSE
200|140 13 03:50:52|TP Start
520|140 13 3129 1 1|No macros defined or no macro tests required
220|140 13 3 03:50:52|NOTINUSE
200|140 14 03:50:52|TP Start
520|140 14 3129 1 1|No macros defined or no macro tests required
220|140 14 3 03:50:52|NOTINUSE
200|140 15 03:50:52|TP Start
520|140 15 3129 1 1|No macros defined or no macro tests required
220|140 15 3 03:50:52|NOTINUSE
410|140 1 15 03:50:52|IC End
80|140 0 03:50:52|TC End, scenario ref 142-0
10|141 /tset/ANSI.os/streamio/Mfgets/T.fgets 03:50:52|TC Start, scenario ref 143-0
15|141 dummy 1|TCM Start
400|141 1 14 03:50:53|IC Start
200|141 1 03:50:53|TP Start
520|141 1 3132 1 1|No macros defined or no macro tests required
220|141 1 3 03:50:53|NOTINUSE
200|141 2 03:50:53|TP Start
520|141 2 3132 1 1|No macros defined or no macro tests required
220|141 2 3 03:50:53|NOTINUSE
200|141 3 03:50:53|TP Start
520|141 3 3132 1 1|No macros defined or no macro tests required
220|141 3 3 03:50:53|NOTINUSE
200|141 4 03:50:53|TP Start
520|141 4 3132 1 1|No macros defined or no macro tests required
220|141 4 3 03:50:53|NOTINUSE
200|141 5 03:50:53|TP Start
520|141 5 3132 1 1|No macros defined or no macro tests required
220|141 5 3 03:50:53|NOTINUSE
200|141 6 03:50:53|TP Start
520|141 6 3132 1 1|No macros defined or no macro tests required
220|141 6 3 03:50:53|NOTINUSE
200|141 7 03:50:53|TP Start
520|141 7 3132 1 1|No macros defined or no macro tests required
220|141 7 3 03:50:53|NOTINUSE
200|141 8 03:50:53|TP Start
520|141 8 3132 1 1|No macros defined or no macro tests required
220|141 8 3 03:50:53|NOTINUSE
200|141 9 03:50:53|TP Start
520|141 9 3132 1 1|No macros defined or no macro tests required
220|141 9 3 03:50:53|NOTINUSE
200|141 10 03:50:53|TP Start
520|141 10 3132 1 1|No macros defined or no macro tests required
220|141 10 3 03:50:53|NOTINUSE
200|141 11 03:50:53|TP Start
520|141 11 3132 1 1|No macros defined or no macro tests required
220|141 11 3 03:50:53|NOTINUSE
200|141 12 03:50:53|TP Start
520|141 12 3132 1 1|No macros defined or no macro tests required
220|141 12 3 03:50:53|NOTINUSE
200|141 13 03:50:53|TP Start
520|141 13 3132 1 1|No macros defined or no macro tests required
220|141 13 3 03:50:53|NOTINUSE
200|141 14 03:50:53|TP Start
520|141 14 3132 1 1|No macros defined or no macro tests required
220|141 14 3 03:50:53|NOTINUSE
410|141 1 14 03:50:53|IC End
80|141 0 03:50:53|TC End, scenario ref 143-0
10|142 /tset/ANSI.os/streamio/Mfopen/T.fopen 03:50:53|TC Start, scenario ref 144-0
15|142 dummy 1|TCM Start
400|142 1 44 03:50:54|IC Start
200|142 1 03:50:54|TP Start
520|142 1 3135 1 1|No macros defined or no macro tests required
220|142 1 3 03:50:54|NOTINUSE
200|142 2 03:50:54|TP Start
520|142 2 3135 1 1|No macros defined or no macro tests required
220|142 2 3 03:50:54|NOTINUSE
200|142 3 03:50:54|TP Start
520|142 3 3135 1 1|No macros defined or no macro tests required
220|142 3 3 03:50:54|NOTINUSE
200|142 4 03:50:54|TP Start
520|142 4 3135 1 1|No macros defined or no macro tests required
220|142 4 3 03:50:54|NOTINUSE
200|142 5 03:50:54|TP Start
520|142 5 3135 1 1|No macros defined or no macro tests required
220|142 5 3 03:50:54|NOTINUSE
200|142 6 03:50:54|TP Start
520|142 6 3135 1 1|No macros defined or no macro tests required
220|142 6 3 03:50:54|NOTINUSE
200|142 7 03:50:54|TP Start
520|142 7 3135 1 1|No macros defined or no macro tests required
220|142 7 3 03:50:54|NOTINUSE
200|142 8 03:50:54|TP Start
520|142 8 3135 1 1|No macros defined or no macro tests required
220|142 8 3 03:50:54|NOTINUSE
200|142 9 03:50:54|TP Start
520|142 9 3135 1 1|No macros defined or no macro tests required
220|142 9 3 03:50:54|NOTINUSE
200|142 10 03:50:54|TP Start
520|142 10 3135 1 1|No macros defined or no macro tests required
220|142 10 3 03:50:54|NOTINUSE
200|142 11 03:50:54|TP Start
520|142 11 3135 1 1|No macros defined or no macro tests required
220|142 11 3 03:50:54|NOTINUSE
200|142 12 03:50:54|TP Start
520|142 12 3135 1 1|No macros defined or no macro tests required
220|142 12 3 03:50:54|NOTINUSE
200|142 13 03:50:54|TP Start
520|142 13 3135 1 1|No macros defined or no macro tests required
220|142 13 3 03:50:54|NOTINUSE
200|142 14 03:50:54|TP Start
520|142 14 3135 1 1|No macros defined or no macro tests required
220|142 14 3 03:50:54|NOTINUSE
200|142 15 03:50:54|TP Start
520|142 15 3135 1 1|No macros defined or no macro tests required
220|142 15 3 03:50:54|NOTINUSE
200|142 16 03:50:54|TP Start
520|142 16 3135 1 1|No macros defined or no macro tests required
220|142 16 3 03:50:54|NOTINUSE
200|142 17 03:50:54|TP Start
520|142 17 3135 1 1|No macros defined or no macro tests required
220|142 17 3 03:50:54|NOTINUSE
200|142 18 03:50:54|TP Start
520|142 18 3135 1 1|No macros defined or no macro tests required
220|142 18 3 03:50:54|NOTINUSE
200|142 19 03:50:54|TP Start
520|142 19 3135 1 1|No macros defined or no macro tests required
220|142 19 3 03:50:54|NOTINUSE
200|142 20 03:50:54|TP Start
520|142 20 3135 1 1|No macros defined or no macro tests required
220|142 20 3 03:50:54|NOTINUSE
200|142 21 03:50:54|TP Start
520|142 21 3135 1 1|No macros defined or no macro tests required
220|142 21 3 03:50:54|NOTINUSE
200|142 22 03:50:54|TP Start
520|142 22 3135 1 1|No macros defined or no macro tests required
220|142 22 3 03:50:54|NOTINUSE
200|142 23 03:50:54|TP Start
520|142 23 3135 1 1|No macros defined or no macro tests required
220|142 23 3 03:50:54|NOTINUSE
200|142 24 03:50:54|TP Start
520|142 24 3135 1 1|No macros defined or no macro tests required
220|142 24 3 03:50:54|NOTINUSE
200|142 25 03:50:54|TP Start
520|142 25 3135 1 1|No macros defined or no macro tests required
220|142 25 3 03:50:54|NOTINUSE
200|142 26 03:50:54|TP Start
520|142 26 3135 1 1|No macros defined or no macro tests required
220|142 26 3 03:50:54|NOTINUSE
200|142 27 03:50:54|TP Start
520|142 27 3135 1 1|No macros defined or no macro tests required
220|142 27 3 03:50:54|NOTINUSE
200|142 28 03:50:54|TP Start
520|142 28 3135 1 1|No macros defined or no macro tests required
220|142 28 3 03:50:54|NOTINUSE
200|142 29 03:50:54|TP Start
520|142 29 3135 1 1|No macros defined or no macro tests required
220|142 29 3 03:50:54|NOTINUSE
200|142 30 03:50:54|TP Start
520|142 30 3135 1 1|No macros defined or no macro tests required
220|142 30 3 03:50:54|NOTINUSE
200|142 31 03:50:54|TP Start
520|142 31 3135 1 1|No macros defined or no macro tests required
220|142 31 3 03:50:54|NOTINUSE
200|142 32 03:50:54|TP Start
520|142 32 3135 1 1|No macros defined or no macro tests required
220|142 32 3 03:50:54|NOTINUSE
200|142 33 03:50:54|TP Start
520|142 33 3135 1 1|No macros defined or no macro tests required
220|142 33 3 03:50:54|NOTINUSE
200|142 34 03:50:54|TP Start
520|142 34 3135 1 1|No macros defined or no macro tests required
220|142 34 3 03:50:54|NOTINUSE
200|142 35 03:50:54|TP Start
520|142 35 3135 1 1|No macros defined or no macro tests required
220|142 35 3 03:50:54|NOTINUSE
200|142 36 03:50:54|TP Start
520|142 36 3135 1 1|No macros defined or no macro tests required
220|142 36 3 03:50:54|NOTINUSE
200|142 37 03:50:54|TP Start
520|142 37 3135 1 1|No macros defined or no macro tests required
220|142 37 3 03:50:54|NOTINUSE
200|142 38 03:50:54|TP Start
520|142 38 3135 1 1|No macros defined or no macro tests required
220|142 38 3 03:50:54|NOTINUSE
200|142 39 03:50:54|TP Start
520|142 39 3135 1 1|No macros defined or no macro tests required
220|142 39 3 03:50:54|NOTINUSE
200|142 40 03:50:54|TP Start
520|142 40 3135 1 1|No macros defined or no macro tests required
220|142 40 3 03:50:54|NOTINUSE
200|142 41 03:50:54|TP Start
520|142 41 3135 1 1|No macros defined or no macro tests required
220|142 41 3 03:50:54|NOTINUSE
200|142 42 03:50:54|TP Start
520|142 42 3135 1 1|No macros defined or no macro tests required
220|142 42 3 03:50:54|NOTINUSE
200|142 43 03:50:54|TP Start
520|142 43 3135 1 1|No macros defined or no macro tests required
220|142 43 3 03:50:54|NOTINUSE
200|142 44 03:50:54|TP Start
520|142 44 3135 1 1|No macros defined or no macro tests required
220|142 44 3 03:50:54|NOTINUSE
410|142 1 44 03:50:54|IC End
80|142 0 03:50:54|TC End, scenario ref 144-0
10|143 /tset/ANSI.os/streamio/Mfopen_X/T.fopen_X 03:50:54|TC Start, scenario ref 145-0
15|143 dummy 1|TCM Start
400|143 1 3 03:50:55|IC Start
200|143 1 03:50:55|TP Start
520|143 1 3138 1 1|No macros defined or no macro tests required
220|143 1 3 03:50:55|NOTINUSE
200|143 2 03:50:55|TP Start
520|143 2 3138 1 1|No macros defined or no macro tests required
220|143 2 3 03:50:55|NOTINUSE
200|143 3 03:50:55|TP Start
520|143 3 3138 1 1|No macros defined or no macro tests required
220|143 3 3 03:50:55|NOTINUSE
410|143 1 3 03:50:55|IC End
80|143 0 03:50:56|TC End, scenario ref 145-0
10|144 /tset/ANSI.os/streamio/Mfputs/T.fputs 03:50:56|TC Start, scenario ref 146-0
15|144 dummy 1|TCM Start
400|144 1 13 03:50:56|IC Start
200|144 1 03:50:56|TP Start
520|144 1 3141 1 1|No macros defined or no macro tests required
220|144 1 3 03:50:56|NOTINUSE
200|144 2 03:50:56|TP Start
520|144 2 3141 1 1|No macros defined or no macro tests required
220|144 2 3 03:50:56|NOTINUSE
200|144 3 03:50:56|TP Start
520|144 3 3141 1 1|No macros defined or no macro tests required
220|144 3 3 03:50:56|NOTINUSE
200|144 4 03:50:56|TP Start
520|144 4 3141 1 1|No macros defined or no macro tests required
220|144 4 3 03:50:56|NOTINUSE
200|144 5 03:50:56|TP Start
520|144 5 3141 1 1|No macros defined or no macro tests required
220|144 5 3 03:50:56|NOTINUSE
200|144 6 03:50:56|TP Start
520|144 6 3141 1 1|No macros defined or no macro tests required
220|144 6 3 03:50:56|NOTINUSE
200|144 7 03:50:56|TP Start
520|144 7 3141 1 1|No macros defined or no macro tests required
220|144 7 3 03:50:56|NOTINUSE
200|144 8 03:50:56|TP Start
520|144 8 3141 1 1|No macros defined or no macro tests required
220|144 8 3 03:50:56|NOTINUSE
200|144 9 03:50:56|TP Start
520|144 9 3141 1 1|No macros defined or no macro tests required
220|144 9 3 03:50:56|NOTINUSE
200|144 10 03:50:56|TP Start
520|144 10 3141 1 1|No macros defined or no macro tests required
220|144 10 3 03:50:56|NOTINUSE
200|144 11 03:50:56|TP Start
520|144 11 3141 1 1|No macros defined or no macro tests required
220|144 11 3 03:50:56|NOTINUSE
200|144 12 03:50:56|TP Start
520|144 12 3141 1 1|No macros defined or no macro tests required
220|144 12 3 03:50:56|NOTINUSE
200|144 13 03:50:56|TP Start
520|144 13 3141 1 1|No macros defined or no macro tests required
220|144 13 3 03:50:56|NOTINUSE
410|144 1 13 03:50:56|IC End
80|144 0 03:50:57|TC End, scenario ref 146-0
10|145 /tset/ANSI.os/streamio/Mfread/T.fread 03:50:57|TC Start, scenario ref 147-0
15|145 dummy 1|TCM Start
400|145 1 16 03:50:57|IC Start
200|145 1 03:50:57|TP Start
520|145 1 3144 1 1|No macros defined or no macro tests required
220|145 1 3 03:50:57|NOTINUSE
200|145 2 03:50:57|TP Start
520|145 2 3144 1 1|No macros defined or no macro tests required
220|145 2 3 03:50:57|NOTINUSE
200|145 3 03:50:57|TP Start
520|145 3 3144 1 1|No macros defined or no macro tests required
220|145 3 3 03:50:57|NOTINUSE
200|145 4 03:50:57|TP Start
520|145 4 3144 1 1|No macros defined or no macro tests required
220|145 4 3 03:50:57|NOTINUSE
200|145 5 03:50:57|TP Start
520|145 5 3144 1 1|No macros defined or no macro tests required
220|145 5 3 03:50:57|NOTINUSE
200|145 6 03:50:57|TP Start
520|145 6 3144 1 1|No macros defined or no macro tests required
220|145 6 3 03:50:57|NOTINUSE
200|145 7 03:50:57|TP Start
520|145 7 3144 1 1|No macros defined or no macro tests required
220|145 7 3 03:50:57|NOTINUSE
200|145 8 03:50:57|TP Start
520|145 8 3144 1 1|No macros defined or no macro tests required
220|145 8 3 03:50:57|NOTINUSE
200|145 9 03:50:57|TP Start
520|145 9 3144 1 1|No macros defined or no macro tests required
220|145 9 3 03:50:57|NOTINUSE
200|145 10 03:50:57|TP Start
520|145 10 3144 1 1|No macros defined or no macro tests required
220|145 10 3 03:50:57|NOTINUSE
200|145 11 03:50:57|TP Start
520|145 11 3144 1 1|No macros defined or no macro tests required
220|145 11 3 03:50:57|NOTINUSE
200|145 12 03:50:57|TP Start
520|145 12 3144 1 1|No macros defined or no macro tests required
220|145 12 3 03:50:57|NOTINUSE
200|145 13 03:50:57|TP Start
520|145 13 3144 1 1|No macros defined or no macro tests required
220|145 13 3 03:50:57|NOTINUSE
200|145 14 03:50:57|TP Start
520|145 14 3144 1 1|No macros defined or no macro tests required
220|145 14 3 03:50:57|NOTINUSE
200|145 15 03:50:57|TP Start
520|145 15 3144 1 1|No macros defined or no macro tests required
220|145 15 3 03:50:57|NOTINUSE
200|145 16 03:50:57|TP Start
520|145 16 3144 1 1|No macros defined or no macro tests required
220|145 16 3 03:50:57|NOTINUSE
410|145 1 16 03:50:57|IC End
80|145 0 03:50:58|TC End, scenario ref 147-0
10|146 /tset/ANSI.os/streamio/Mfreopen/T.freopen 03:50:58|TC Start, scenario ref 148-0
15|146 dummy 1|TCM Start
400|146 1 49 03:50:58|IC Start
200|146 1 03:50:58|TP Start
520|146 1 3147 1 1|No macros defined or no macro tests required
220|146 1 3 03:50:58|NOTINUSE
200|146 2 03:50:58|TP Start
520|146 2 3147 1 1|No macros defined or no macro tests required
220|146 2 3 03:50:58|NOTINUSE
200|146 3 03:50:58|TP Start
520|146 3 3147 1 1|No macros defined or no macro tests required
220|146 3 3 03:50:58|NOTINUSE
200|146 4 03:50:58|TP Start
520|146 4 3147 1 1|No macros defined or no macro tests required
220|146 4 3 03:50:58|NOTINUSE
200|146 5 03:50:58|TP Start
520|146 5 3147 1 1|No macros defined or no macro tests required
220|146 5 3 03:50:58|NOTINUSE
200|146 6 03:50:58|TP Start
520|146 6 3147 1 1|No macros defined or no macro tests required
220|146 6 3 03:50:58|NOTINUSE
200|146 7 03:50:58|TP Start
520|146 7 3147 1 1|No macros defined or no macro tests required
220|146 7 3 03:50:58|NOTINUSE
200|146 8 03:50:58|TP Start
520|146 8 3147 1 1|No macros defined or no macro tests required
220|146 8 3 03:50:58|NOTINUSE
200|146 9 03:50:58|TP Start
520|146 9 3147 1 1|No macros defined or no macro tests required
220|146 9 3 03:50:58|NOTINUSE
200|146 10 03:50:58|TP Start
520|146 10 3147 1 1|No macros defined or no macro tests required
220|146 10 3 03:50:58|NOTINUSE
200|146 11 03:50:58|TP Start
520|146 11 3147 1 1|No macros defined or no macro tests required
220|146 11 3 03:50:58|NOTINUSE
200|146 12 03:50:58|TP Start
520|146 12 3147 1 1|No macros defined or no macro tests required
220|146 12 3 03:50:58|NOTINUSE
200|146 13 03:50:58|TP Start
520|146 13 3147 1 1|No macros defined or no macro tests required
220|146 13 3 03:50:58|NOTINUSE
200|146 14 03:50:58|TP Start
520|146 14 3147 1 1|No macros defined or no macro tests required
220|146 14 3 03:50:58|NOTINUSE
200|146 15 03:50:58|TP Start
520|146 15 3147 1 1|No macros defined or no macro tests required
220|146 15 3 03:50:58|NOTINUSE
200|146 16 03:50:58|TP Start
520|146 16 3147 1 1|No macros defined or no macro tests required
220|146 16 3 03:50:58|NOTINUSE
200|146 17 03:50:58|TP Start
520|146 17 3147 1 1|No macros defined or no macro tests required
220|146 17 3 03:50:58|NOTINUSE
200|146 18 03:50:58|TP Start
520|146 18 3147 1 1|No macros defined or no macro tests required
220|146 18 3 03:50:58|NOTINUSE
200|146 19 03:50:58|TP Start
520|146 19 3147 1 1|No macros defined or no macro tests required
220|146 19 3 03:50:58|NOTINUSE
200|146 20 03:50:58|TP Start
520|146 20 3147 1 1|No macros defined or no macro tests required
220|146 20 3 03:50:58|NOTINUSE
200|146 21 03:50:58|TP Start
520|146 21 3147 1 1|No macros defined or no macro tests required
220|146 21 3 03:50:58|NOTINUSE
200|146 22 03:50:58|TP Start
520|146 22 3147 1 1|No macros defined or no macro tests required
220|146 22 3 03:50:58|NOTINUSE
200|146 23 03:50:58|TP Start
520|146 23 3147 1 1|No macros defined or no macro tests required
220|146 23 3 03:50:58|NOTINUSE
200|146 24 03:50:58|TP Start
520|146 24 3147 1 1|No macros defined or no macro tests required
220|146 24 3 03:50:58|NOTINUSE
200|146 25 03:50:58|TP Start
520|146 25 3147 1 1|No macros defined or no macro tests required
220|146 25 3 03:50:58|NOTINUSE
200|146 26 03:50:58|TP Start
520|146 26 3147 1 1|No macros defined or no macro tests required
220|146 26 3 03:50:58|NOTINUSE
200|146 27 03:50:58|TP Start
520|146 27 3147 1 1|No macros defined or no macro tests required
220|146 27 3 03:50:58|NOTINUSE
200|146 28 03:50:58|TP Start
520|146 28 3147 1 1|No macros defined or no macro tests required
220|146 28 3 03:50:58|NOTINUSE
200|146 29 03:50:58|TP Start
520|146 29 3147 1 1|No macros defined or no macro tests required
220|146 29 3 03:50:58|NOTINUSE
200|146 30 03:50:58|TP Start
520|146 30 3147 1 1|No macros defined or no macro tests required
220|146 30 3 03:50:58|NOTINUSE
200|146 31 03:50:58|TP Start
520|146 31 3147 1 1|No macros defined or no macro tests required
220|146 31 3 03:50:58|NOTINUSE
200|146 32 03:50:58|TP Start
520|146 32 3147 1 1|No macros defined or no macro tests required
220|146 32 3 03:50:58|NOTINUSE
200|146 33 03:50:58|TP Start
520|146 33 3147 1 1|No macros defined or no macro tests required
220|146 33 3 03:50:58|NOTINUSE
200|146 34 03:50:58|TP Start
520|146 34 3147 1 1|No macros defined or no macro tests required
220|146 34 3 03:50:58|NOTINUSE
200|146 35 03:50:58|TP Start
520|146 35 3147 1 1|No macros defined or no macro tests required
220|146 35 3 03:50:58|NOTINUSE
200|146 36 03:50:58|TP Start
520|146 36 3147 1 1|No macros defined or no macro tests required
220|146 36 3 03:50:58|NOTINUSE
200|146 37 03:50:58|TP Start
520|146 37 3147 1 1|No macros defined or no macro tests required
220|146 37 3 03:50:58|NOTINUSE
200|146 38 03:50:58|TP Start
520|146 38 3147 1 1|No macros defined or no macro tests required
220|146 38 3 03:50:58|NOTINUSE
200|146 39 03:50:58|TP Start
520|146 39 3147 1 1|No macros defined or no macro tests required
220|146 39 3 03:50:58|NOTINUSE
200|146 40 03:50:58|TP Start
520|146 40 3147 1 1|No macros defined or no macro tests required
220|146 40 3 03:50:58|NOTINUSE
200|146 41 03:50:58|TP Start
520|146 41 3147 1 1|No macros defined or no macro tests required
220|146 41 3 03:50:58|NOTINUSE
200|146 42 03:50:58|TP Start
520|146 42 3147 1 1|No macros defined or no macro tests required
220|146 42 3 03:50:58|NOTINUSE
200|146 43 03:50:58|TP Start
520|146 43 3147 1 1|No macros defined or no macro tests required
220|146 43 3 03:50:58|NOTINUSE
200|146 44 03:50:58|TP Start
520|146 44 3147 1 1|No macros defined or no macro tests required
220|146 44 3 03:50:58|NOTINUSE
200|146 45 03:50:58|TP Start
520|146 45 3147 1 1|No macros defined or no macro tests required
220|146 45 3 03:50:58|NOTINUSE
200|146 46 03:50:58|TP Start
520|146 46 3147 1 1|No macros defined or no macro tests required
220|146 46 3 03:50:58|NOTINUSE
200|146 47 03:50:58|TP Start
520|146 47 3147 1 1|No macros defined or no macro tests required
220|146 47 3 03:50:58|NOTINUSE
200|146 48 03:50:58|TP Start
520|146 48 3147 1 1|No macros defined or no macro tests required
220|146 48 3 03:50:58|NOTINUSE
200|146 49 03:50:58|TP Start
520|146 49 3147 1 1|No macros defined or no macro tests required
220|146 49 3 03:50:58|NOTINUSE
410|146 1 49 03:50:58|IC End
80|146 0 03:50:59|TC End, scenario ref 148-0
10|147 /tset/ANSI.os/streamio/Mfreopen_X/T.freopen_X 03:50:59|TC Start, scenario ref 149-0
15|147 dummy 1|TCM Start
400|147 1 3 03:50:59|IC Start
200|147 1 03:50:59|TP Start
520|147 1 3150 1 1|No macros defined or no macro tests required
220|147 1 3 03:50:59|NOTINUSE
200|147 2 03:50:59|TP Start
520|147 2 3150 1 1|No macros defined or no macro tests required
220|147 2 3 03:50:59|NOTINUSE
200|147 3 03:50:59|TP Start
520|147 3 3150 1 1|No macros defined or no macro tests required
220|147 3 3 03:50:59|NOTINUSE
410|147 1 3 03:50:59|IC End
80|147 0 03:51:00|TC End, scenario ref 149-0
10|148 /tset/ANSI.os/streamio/Mfseek/T.fseek 03:51:00|TC Start, scenario ref 150-0
15|148 dummy 1|TCM Start
400|148 1 17 03:51:00|IC Start
200|148 1 03:51:00|TP Start
520|148 1 3153 1 1|No macros defined or no macro tests required
220|148 1 3 03:51:00|NOTINUSE
200|148 2 03:51:00|TP Start
520|148 2 3153 1 1|No macros defined or no macro tests required
220|148 2 3 03:51:00|NOTINUSE
200|148 3 03:51:00|TP Start
520|148 3 3153 1 1|No macros defined or no macro tests required
220|148 3 3 03:51:00|NOTINUSE
200|148 4 03:51:00|TP Start
520|148 4 3153 1 1|No macros defined or no macro tests required
220|148 4 3 03:51:00|NOTINUSE
200|148 5 03:51:00|TP Start
520|148 5 3153 1 1|No macros defined or no macro tests required
220|148 5 3 03:51:00|NOTINUSE
200|148 6 03:51:00|TP Start
520|148 6 3153 1 1|No macros defined or no macro tests required
220|148 6 3 03:51:00|NOTINUSE
200|148 7 03:51:00|TP Start
520|148 7 3153 1 1|No macros defined or no macro tests required
220|148 7 3 03:51:00|NOTINUSE
200|148 8 03:51:00|TP Start
520|148 8 3153 1 1|No macros defined or no macro tests required
220|148 8 3 03:51:00|NOTINUSE
200|148 9 03:51:00|TP Start
520|148 9 3153 1 1|No macros defined or no macro tests required
220|148 9 3 03:51:00|NOTINUSE
200|148 10 03:51:00|TP Start
520|148 10 3153 1 1|No macros defined or no macro tests required
220|148 10 3 03:51:00|NOTINUSE
200|148 11 03:51:00|TP Start
520|148 11 3153 1 1|No macros defined or no macro tests required
220|148 11 3 03:51:00|NOTINUSE
200|148 12 03:51:00|TP Start
520|148 12 3153 1 1|No macros defined or no macro tests required
220|148 12 3 03:51:00|NOTINUSE
200|148 13 03:51:00|TP Start
520|148 13 3153 1 1|No macros defined or no macro tests required
220|148 13 3 03:51:00|NOTINUSE
200|148 14 03:51:00|TP Start
520|148 14 3153 1 1|No macros defined or no macro tests required
220|148 14 3 03:51:00|NOTINUSE
200|148 15 03:51:00|TP Start
520|148 15 3153 1 1|No macros defined or no macro tests required
220|148 15 3 03:51:00|NOTINUSE
200|148 16 03:51:00|TP Start
520|148 16 3153 1 1|No macros defined or no macro tests required
220|148 16 3 03:51:00|NOTINUSE
200|148 17 03:51:00|TP Start
520|148 17 3153 1 1|No macros defined or no macro tests required
220|148 17 3 03:51:00|NOTINUSE
410|148 1 17 03:51:00|IC End
80|148 0 03:51:01|TC End, scenario ref 150-0
10|149 /tset/ANSI.os/streamio/Mftell/T.ftell 03:51:01|TC Start, scenario ref 151-0
15|149 dummy 1|TCM Start
400|149 1 4 03:51:01|IC Start
200|149 1 03:51:01|TP Start
520|149 1 3156 1 1|No macros defined or no macro tests required
220|149 1 3 03:51:01|NOTINUSE
200|149 2 03:51:01|TP Start
520|149 2 3156 1 1|No macros defined or no macro tests required
220|149 2 3 03:51:01|NOTINUSE
200|149 3 03:51:01|TP Start
520|149 3 3156 1 1|No macros defined or no macro tests required
220|149 3 3 03:51:01|NOTINUSE
200|149 4 03:51:01|TP Start
520|149 4 3156 1 1|No macros defined or no macro tests required
220|149 4 3 03:51:01|NOTINUSE
410|149 1 4 03:51:01|IC End
80|149 0 03:51:02|TC End, scenario ref 151-0
10|150 /tset/ANSI.os/streamio/Mfwrite/T.fwrite 03:51:02|TC Start, scenario ref 152-0
15|150 dummy 1|TCM Start
400|150 1 19 03:51:02|IC Start
200|150 1 03:51:02|TP Start
520|150 1 3159 1 1|No macros defined or no macro tests required
220|150 1 3 03:51:02|NOTINUSE
200|150 2 03:51:02|TP Start
520|150 2 3159 1 1|No macros defined or no macro tests required
220|150 2 3 03:51:02|NOTINUSE
200|150 3 03:51:02|TP Start
520|150 3 3159 1 1|No macros defined or no macro tests required
220|150 3 3 03:51:02|NOTINUSE
200|150 4 03:51:02|TP Start
520|150 4 3159 1 1|No macros defined or no macro tests required
220|150 4 3 03:51:02|NOTINUSE
200|150 5 03:51:02|TP Start
520|150 5 3159 1 1|No macros defined or no macro tests required
220|150 5 3 03:51:02|NOTINUSE
200|150 6 03:51:02|TP Start
520|150 6 3159 1 1|No macros defined or no macro tests required
220|150 6 3 03:51:02|NOTINUSE
200|150 7 03:51:02|TP Start
520|150 7 3159 1 1|No macros defined or no macro tests required
220|150 7 3 03:51:02|NOTINUSE
200|150 8 03:51:02|TP Start
520|150 8 3159 1 1|No macros defined or no macro tests required
220|150 8 3 03:51:02|NOTINUSE
200|150 9 03:51:02|TP Start
520|150 9 3159 1 1|No macros defined or no macro tests required
220|150 9 3 03:51:02|NOTINUSE
200|150 10 03:51:02|TP Start
520|150 10 3159 1 1|No macros defined or no macro tests required
220|150 10 3 03:51:02|NOTINUSE
200|150 11 03:51:02|TP Start
520|150 11 3159 1 1|No macros defined or no macro tests required
220|150 11 3 03:51:02|NOTINUSE
200|150 12 03:51:02|TP Start
520|150 12 3159 1 1|No macros defined or no macro tests required
220|150 12 3 03:51:02|NOTINUSE
200|150 13 03:51:02|TP Start
520|150 13 3159 1 1|No macros defined or no macro tests required
220|150 13 3 03:51:02|NOTINUSE
200|150 14 03:51:02|TP Start
520|150 14 3159 1 1|No macros defined or no macro tests required
220|150 14 3 03:51:02|NOTINUSE
200|150 15 03:51:02|TP Start
520|150 15 3159 1 1|No macros defined or no macro tests required
220|150 15 3 03:51:02|NOTINUSE
200|150 16 03:51:02|TP Start
520|150 16 3159 1 1|No macros defined or no macro tests required
220|150 16 3 03:51:02|NOTINUSE
200|150 17 03:51:02|TP Start
520|150 17 3159 1 1|No macros defined or no macro tests required
220|150 17 3 03:51:02|NOTINUSE
200|150 18 03:51:02|TP Start
520|150 18 3159 1 1|No macros defined or no macro tests required
220|150 18 3 03:51:02|NOTINUSE
200|150 19 03:51:02|TP Start
520|150 19 3159 1 1|No macros defined or no macro tests required
220|150 19 3 03:51:02|NOTINUSE
410|150 1 19 03:51:02|IC End
80|150 0 03:51:03|TC End, scenario ref 152-0
10|151 /tset/ANSI.os/streamio/Mgetc/T.fgetc 03:51:03|TC Start, scenario ref 153-0
15|151 3.6-lite 13|TCM Start
400|151 1 1 03:51:03|IC Start
200|151 1 03:51:03|TP Start
220|151 1 0 03:51:03|PASS
410|151 1 1 03:51:03|IC End
400|151 2 1 03:51:03|IC Start
200|151 2 03:51:03|TP Start
220|151 2 0 03:51:03|PASS
410|151 2 1 03:51:03|IC End
400|151 3 1 03:51:03|IC Start
200|151 3 03:51:03|TP Start
220|151 3 0 03:51:03|PASS
410|151 3 1 03:51:03|IC End
400|151 4 1 03:51:03|IC Start
200|151 4 03:51:03|TP Start
220|151 4 0 03:51:05|PASS
410|151 4 1 03:51:05|IC End
400|151 5 1 03:51:05|IC Start
200|151 5 03:51:05|TP Start
220|151 5 0 03:51:05|PASS
410|151 5 1 03:51:05|IC End
400|151 6 1 03:51:05|IC Start
200|151 6 03:51:05|TP Start
220|151 6 0 03:51:05|PASS
410|151 6 1 03:51:05|IC End
400|151 7 1 03:51:05|IC Start
200|151 7 03:51:05|TP Start
220|151 7 0 03:51:05|PASS
410|151 7 1 03:51:05|IC End
400|151 8 1 03:51:05|IC Start
200|151 8 03:51:05|TP Start
220|151 8 0 03:51:30|PASS
410|151 8 1 03:51:30|IC End
400|151 9 1 03:51:30|IC Start
200|151 9 03:51:30|TP Start
220|151 9 0 03:51:44|PASS
410|151 9 1 03:51:44|IC End
400|151 10 1 03:51:44|IC Start
200|151 10 03:51:44|TP Start
220|151 10 0 03:52:16|PASS
410|151 10 1 03:52:16|IC End
400|151 11 1 03:52:16|IC Start
200|151 11 03:52:16|TP Start
220|151 11 0 03:52:18|PASS
410|151 11 1 03:52:18|IC End
400|151 12 1 03:52:18|IC Start
200|151 12 03:52:18|TP Start
220|151 12 3 03:52:18|NOTINUSE
410|151 12 1 03:52:18|IC End
400|151 13 1 03:52:18|IC Start
200|151 13 03:52:18|TP Start
220|151 13 3 03:52:18|NOTINUSE
410|151 13 1 03:52:18|IC End
80|151 0 03:52:20|TC End, scenario ref 153-0
10|152 /tset/ANSI.os/streamio/Mgetc/T.getc 03:52:20|TC Start, scenario ref 154-0
15|152 3.6-lite 13|TCM Start
400|152 1 1 03:52:20|IC Start
200|152 1 03:52:20|TP Start
220|152 1 0 03:52:20|PASS
410|152 1 1 03:52:20|IC End
400|152 2 1 03:52:20|IC Start
200|152 2 03:52:20|TP Start
220|152 2 0 03:52:20|PASS
410|152 2 1 03:52:20|IC End
400|152 3 1 03:52:20|IC Start
200|152 3 03:52:20|TP Start
220|152 3 0 03:52:20|PASS
410|152 3 1 03:52:20|IC End
400|152 4 1 03:52:20|IC Start
200|152 4 03:52:20|TP Start
220|152 4 0 03:52:22|PASS
410|152 4 1 03:52:22|IC End
400|152 5 1 03:52:22|IC Start
200|152 5 03:52:22|TP Start
220|152 5 0 03:52:22|PASS
410|152 5 1 03:52:22|IC End
400|152 6 1 03:52:22|IC Start
200|152 6 03:52:22|TP Start
220|152 6 0 03:52:22|PASS
410|152 6 1 03:52:22|IC End
400|152 7 1 03:52:22|IC Start
200|152 7 03:52:22|TP Start
220|152 7 0 03:52:22|PASS
410|152 7 1 03:52:22|IC End
400|152 8 1 03:52:22|IC Start
200|152 8 03:52:22|TP Start
220|152 8 0 03:52:47|PASS
410|152 8 1 03:52:47|IC End
400|152 9 1 03:52:47|IC Start
200|152 9 03:52:47|TP Start
220|152 9 0 03:53:01|PASS
410|152 9 1 03:53:01|IC End
400|152 10 1 03:53:01|IC Start
200|152 10 03:53:01|TP Start
220|152 10 0 03:53:33|PASS
410|152 10 1 03:53:33|IC End
400|152 11 1 03:53:33|IC Start
200|152 11 03:53:33|TP Start
220|152 11 0 03:53:35|PASS
410|152 11 1 03:53:35|IC End
400|152 12 1 03:53:35|IC Start
200|152 12 03:53:35|TP Start
220|152 12 3 03:53:35|NOTINUSE
410|152 12 1 03:53:35|IC End
400|152 13 1 03:53:35|IC Start
200|152 13 03:53:35|TP Start
220|152 13 3 03:53:35|NOTINUSE
410|152 13 1 03:53:35|IC End
80|152 0 03:53:37|TC End, scenario ref 154-0
10|153 /tset/ANSI.os/streamio/Mgetc/T.getchar 03:53:37|TC Start, scenario ref 155-0
15|153 3.6-lite 13|TCM Start
400|153 1 1 03:53:37|IC Start
200|153 1 03:53:37|TP Start
220|153 1 0 03:53:37|PASS
410|153 1 1 03:53:37|IC End
400|153 2 1 03:53:37|IC Start
200|153 2 03:53:37|TP Start
220|153 2 0 03:53:37|PASS
410|153 2 1 03:53:37|IC End
400|153 3 1 03:53:37|IC Start
200|153 3 03:53:37|TP Start
220|153 3 0 03:53:37|PASS
410|153 3 1 03:53:37|IC End
400|153 4 1 03:53:37|IC Start
200|153 4 03:53:37|TP Start
220|153 4 0 03:53:39|PASS
410|153 4 1 03:53:39|IC End
400|153 5 1 03:53:39|IC Start
200|153 5 03:53:39|TP Start
220|153 5 0 03:53:39|PASS
410|153 5 1 03:53:39|IC End
400|153 6 1 03:53:39|IC Start
200|153 6 03:53:39|TP Start
220|153 6 0 03:53:39|PASS
410|153 6 1 03:53:39|IC End
400|153 7 1 03:53:39|IC Start
200|153 7 03:53:39|TP Start
220|153 7 0 03:53:39|PASS
410|153 7 1 03:53:39|IC End
400|153 8 1 03:53:39|IC Start
200|153 8 03:53:39|TP Start
220|153 8 0 03:54:04|PASS
410|153 8 1 03:54:04|IC End
400|153 9 1 03:54:04|IC Start
200|153 9 03:54:04|TP Start
220|153 9 0 03:54:18|PASS
410|153 9 1 03:54:18|IC End
400|153 10 1 03:54:18|IC Start
200|153 10 03:54:18|TP Start
220|153 10 0 03:54:50|PASS
410|153 10 1 03:54:50|IC End
400|153 11 1 03:54:50|IC Start
200|153 11 03:54:50|TP Start
220|153 11 0 03:54:52|PASS
410|153 11 1 03:54:52|IC End
400|153 12 1 03:54:52|IC Start
200|153 12 03:54:52|TP Start
220|153 12 3 03:54:52|NOTINUSE
410|153 12 1 03:54:52|IC End
400|153 13 1 03:54:52|IC Start
200|153 13 03:54:52|TP Start
220|153 13 3 03:54:52|NOTINUSE
410|153 13 1 03:54:52|IC End
80|153 0 03:54:54|TC End, scenario ref 155-0
10|154 /tset/ANSI.os/streamio/Mgets/T.gets 03:54:54|TC Start, scenario ref 156-0
15|154 dummy 1|TCM Start
400|154 1 14 03:54:54|IC Start
200|154 1 03:54:54|TP Start
520|154 1 3249 1 1|No macros defined or no macro tests required
220|154 1 3 03