diff -Nru gcc15-new4/gcc-snapshot-20240829/debian/patches/sh-enable-lra.diff gcc15-new3/gcc-snapshot-20240829/debian/patches/sh-enable-lra.diff --- gcc15-new4/gcc-snapshot-20240829/debian/patches/sh-enable-lra.diff 1970-01-01 01:00:00.000000000 +0100 +++ gcc15-new3/gcc-snapshot-20240829/debian/patches/sh-enable-lra.diff 2024-09-12 22:31:35.238265781 +0200 @@ -0,0 +1,23 @@ +From b0a8a63b1f030dcb2e00fc8061839826b869abb8 Mon Sep 17 00:00:00 2001 +From: John Paul Adrian Glaubitz +Date: Wed, 11 Sep 2024 11:37:20 +0200 +Subject: [PATCH 2/2] Enable LRA by default on SH + +--- + gcc/config/sh/sh.opt | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/gcc/config/sh/sh.opt b/src/gcc/config/sh/sh.opt +index c44cfe70cb1..718dfb744ff 100644 +--- a/src/gcc/config/sh/sh.opt ++++ b/src/gcc/config/sh/sh.opt +@@ -299,5 +299,5 @@ Target Var(TARGET_FSRRA) + Enable the use of the fsrra instruction. + + mlra +-Target Var(sh_lra_flag) Init(0) Save ++Target Var(sh_lra_flag) Init(1) Save + Use LRA instead of reload (transitional). +-- +2.45.2 + diff -Nru gcc15-new4/gcc-snapshot-20240829/debian/patches/sh-lra-support.diff gcc15-new3/gcc-snapshot-20240829/debian/patches/sh-lra-support.diff --- gcc15-new4/gcc-snapshot-20240829/debian/patches/sh-lra-support.diff 1970-01-01 01:00:00.000000000 +0100 +++ gcc15-new3/gcc-snapshot-20240829/debian/patches/sh-lra-support.diff 2024-09-12 22:31:30.810123013 +0200 @@ -0,0 +1,336 @@ +From 6f26c601ee6200730f03c14755d65e431d1916e8 Mon Sep 17 00:00:00 2001 +From: John Paul Adrian Glaubitz +Date: Mon, 2 Sep 2024 19:38:48 +0200 +Subject: [PATCH 1/2] SH: Add support for LRA + +--- + gcc/config/sh/sh-mem.cc | 6 ++ + gcc/config/sh/sh-protos.h | 1 + + gcc/config/sh/sh.cc | 23 ++++--- + gcc/config/sh/sh.md | 133 ++++++++++++++++++++++++++++++++------ + 4 files changed, 135 insertions(+), 28 deletions(-) + +diff --git a/src/gcc/config/sh/sh-mem.cc b/src/gcc/config/sh/sh-mem.cc +index e22419912d6..3adc037c008 100644 +--- a/src/gcc/config/sh/sh-mem.cc ++++ b/src/gcc/config/sh/sh-mem.cc +@@ -135,6 +135,12 @@ expand_block_move (rtx *operands) + int dwords = bytes >> 3; + emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1))); + emit_insn (gen_block_lump_real_i4 (func_addr_rtx, lab)); ++ if (sh_lra_p ()) ++ { ++ emit_clobber (r4); ++ emit_clobber (r5); ++ emit_clobber (r6); ++ } + return true; + } + else +diff --git a/src/gcc/config/sh/sh-protos.h b/src/gcc/config/sh/sh-protos.h +index b151a7c8fcc..5e5bd0aff7e 100644 +--- a/src/gcc/config/sh/sh-protos.h ++++ b/src/gcc/config/sh/sh-protos.h +@@ -61,6 +61,7 @@ extern rtx legitimize_pic_address (rtx, machine_mode, rtx); + extern bool nonpic_symbol_mentioned_p (rtx); + extern void output_pic_addr_const (FILE *, rtx); + extern bool expand_block_move (rtx *); ++extern bool sh_satisfies_constraint_Sid_subreg_index (rtx); + extern void prepare_move_operands (rtx[], machine_mode mode); + extern bool sh_expand_cmpstr (rtx *); + extern bool sh_expand_cmpnstr (rtx *); +diff --git a/src/gcc/config/sh/sh.cc b/src/gcc/config/sh/sh.cc +index 7391b8df583..3fcd2acd1e5 100644 +--- a/src/gcc/config/sh/sh.cc ++++ b/src/gcc/config/sh/sh.cc +@@ -1577,6 +1577,18 @@ sh_encode_section_info (tree decl, rtx rtl, int first) + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION; + } + ++/* Test Sid constraint with subreg index. See also the comment in ++ prepare_move_operands. */ ++bool ++sh_satisfies_constraint_Sid_subreg_index (rtx op) ++{ ++ return ((GET_CODE (op) == MEM) ++ && ((GET_CODE (XEXP (op, 0)) == PLUS) ++ && ((GET_CODE (XEXP (XEXP (op, 0), 0)) == REG) ++ && ((GET_CODE (XEXP (XEXP (op, 0), 1)) == SUBREG) ++ && (GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 0)) == REG))))); ++} ++ + /* Prepare operands for a move define_expand; specifically, one of the + operands must be in a register. */ + void +@@ -4820,6 +4832,7 @@ broken_move (rtx_insn *insn) + we changed this to do a constant load. In that case + we don't have an r0 clobber, hence we must use fldi. */ + && (TARGET_FMOVD ++ || sh_lra_p () + || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) + == SCRATCH)) + && REG_P (SET_DEST (pat)) +@@ -11448,16 +11461,6 @@ sh_legitimize_address_displacement (rtx *offset1, rtx *offset2, + bool + sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2) + { +- /* op0 == op1 */ +- if (rtx_equal_p (op0, op1)) +- return true; +- /* fy, FQ, reg */ +- if (GET_CODE (op1) == CONST_DOUBLE +- && ! satisfies_constraint_G (op1) +- && ! satisfies_constraint_H (op1) +- && REG_P (op0) +- && REG_P (op2)) +- return true; + /* f, r, y */ + if (REG_P (op0) && FP_REGISTER_P (REGNO (op0)) + && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1)) +diff --git a/src/gcc/config/sh/sh.md b/src/gcc/config/sh/sh.md +index 7eee12ca6b8..ef65777223c 100644 +--- a/src/gcc/config/sh/sh.md ++++ b/src/gcc/config/sh/sh.md +@@ -4801,7 +4801,38 @@ + + (define_expand "extendsi2" + [(set (match_operand:SI 0 "arith_reg_dest") +- (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))]) ++ (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))] ++ "" ++{ ++ /* When the displacement addressing is used, RA will assign r0 to ++ the pseudo register operand for the QI/HImode load. See ++ the comment in sh.cc:prepare_move_operand and PR target/55212. */ ++ if (! lra_in_progress && ! reload_completed ++ && sh_lra_p () ++ && ! TARGET_SH2A ++ && arith_reg_dest (operands[0], mode) ++ && short_displacement_mem_operand (operands[1], mode)) ++ { ++ emit_insn (gen_extendsi2_short_mem_disp_z (operands[0], ++ operands[1])); ++ DONE; ++ } ++}) ++ ++(define_insn_and_split "extendsi2_short_mem_disp_z" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=r") ++ (sign_extend:SI ++ (match_operand:QIHI 1 "short_displacement_mem_operand" "m"))) ++ (clobber (reg:SI R0_REG))] ++ "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()" ++ "#" ++ "&& 1" ++ [(set (match_dup 2) (sign_extend:SI (match_dup 1))) ++ (set (match_dup 0) (match_dup 2))] ++{ ++ operands[2] = gen_rtx_REG (SImode, R0_REG); ++} ++ [(set_attr "type" "load")]) + + (define_insn_and_split "*extendsi2_compact_reg" + [(set (match_operand:SI 0 "arith_reg_dest" "=r") +@@ -5343,9 +5374,50 @@ + operands[1] = gen_lowpart (mode, reg); + } + ++ if (! lra_in_progress && ! reload_completed ++ && sh_lra_p () ++ && ! TARGET_SH2A ++ && arith_reg_operand (operands[1], mode) ++ && (satisfies_constraint_Sid (operands[0]) ++ || sh_satisfies_constraint_Sid_subreg_index (operands[0]))) ++ { ++ rtx adr = XEXP (operands[0], 0); ++ rtx base = XEXP (adr, 0); ++ rtx idx = XEXP (adr, 1); ++ emit_insn (gen_mov_store_mem_index (base, idx, ++ operands[1])); ++ DONE; ++ } ++ + prepare_move_operands (operands, mode); + }) + ++(define_insn "*mov_store_mem_index" ++ [(set (mem:QIHI ++ (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r") ++ (match_operand:SI 1 "arith_reg_operand" "z"))) ++ (match_operand:QIHI 2 "arith_reg_operand" "r"))] ++ "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p () ++ && REG_P (operands[1]) && REGNO (operands[1]) == R0_REG" ++ "mov. %2,@(%1,%0)" ++ [(set_attr "type" "store")]) ++ ++(define_insn_and_split "mov_store_mem_index" ++ [(set (mem:QIHI ++ (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r") ++ (match_operand:SI 1 "arith_reg_operand" "^zr"))) ++ (match_operand:QIHI 2 "arith_reg_operand" "r")) ++ (clobber (reg:SI R0_REG))] ++ "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()" ++ "#" ++ "&& 1" ++ [(set (match_dup 3) (match_dup 1)) ++ (set (mem:QIHI (plus:SI (match_dup 0) (match_dup 3))) (match_dup 2))] ++{ ++ operands[3] = gen_rtx_REG (SImode, R0_REG); ++} ++ [(set_attr "type" "store")]) ++ + ;; The pre-dec and post-inc mems must be captured by the '<' and '>' + ;; constraints, otherwise wrong code might get generated. + (define_insn "*mov_load_predec" +@@ -6145,8 +6217,7 @@ + (match_operand:SF 1 "general_movsrc_operand" + " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y")) + (use (reg:SI FPSCR_MODES_REG)) +- (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r")) +- (const_int 0)] ++ (clobber (match_scratch:SF 2 "=f,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))] + "TARGET_SH2E + && (arith_reg_operand (operands[0], SFmode) + || fpul_operand (operands[0], SFmode) +@@ -6233,12 +6304,24 @@ + (const_string "none") + (const_string "none")])]) + ++(define_insn "movsf_ie_const_ra" ++ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") ++ (match_operand:SF 1 "const_double_operand" "F")) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (clobber (reg:SI R0_REG))] ++ "TARGET_SH2E && sh_lra_p ()" ++ "#" ++ [(set_attr "type" "pcfload") ++ (set_attr "length" "4")]) ++ + (define_split + [(set (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "register_operand" "")) + (use (reg:SI FPSCR_MODES_REG)) + (clobber (reg:SI FPUL_REG))] +- "TARGET_SH1" ++ "TARGET_SH1 ++ && ! fpul_operand (operands[0], SFmode) ++ && ! fpul_operand (operands[1], SFmode)" + [(parallel [(set (reg:SF FPUL_REG) (match_dup 1)) + (use (reg:SI FPSCR_MODES_REG)) + (clobber (scratch:SI))]) +@@ -6255,13 +6338,23 @@ + prepare_move_operands (operands, SFmode); + if (TARGET_SH2E) + { +- if (lra_in_progress) ++ if (lra_in_progress && ++ !(REG_P (operands[0]) && REG_P (operands[1]))) + { + if (GET_CODE (operands[0]) == SCRATCH) + DONE; + emit_insn (gen_movsf_ie_ra (operands[0], operands[1])); + DONE; + } ++ else if (sh_lra_p () ++ && GET_CODE (operands[1]) == CONST_DOUBLE ++ && ! satisfies_constraint_G (operands[1]) ++ && ! satisfies_constraint_H (operands[1]) ++ && REG_P (operands[0])) ++ { ++ emit_insn (gen_movsf_ie_const_ra (operands[0], operands[1])); ++ DONE; ++ } + + emit_insn (gen_movsf_ie (operands[0], operands[1])); + DONE; +@@ -6563,16 +6656,17 @@ + (use (reg:SI FPSCR_MODES_REG)) + (use (reg:SI PIC_REG)) + (clobber (reg:SI PR_REG)) +- (clobber (match_scratch:SI 2 "=&r"))] ++ (clobber (reg:SI R1_REG))] + "TARGET_SH2" + "#" + "reload_completed" + [(const_int 0)] + { + rtx lab = PATTERN (gen_call_site ()); +- +- sh_expand_sym_label2reg (operands[2], operands[0], lab, false); +- emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab))); ++ rtx scr = gen_rtx_REG (Pmode, R1_REG); ++ ++ sh_expand_sym_label2reg (scr, operands[0], lab, false); ++ emit_call_insn (gen_calli_pcrel (scr, operands[1], copy_rtx (lab))); + DONE; + } + [(set_attr "type" "call") +@@ -6675,16 +6769,17 @@ + (use (reg:SI FPSCR_MODES_REG)) + (use (reg:SI PIC_REG)) + (clobber (reg:SI PR_REG)) +- (clobber (match_scratch:SI 3 "=&r"))] ++ (clobber (reg:SI R1_REG))] + "TARGET_SH2" + "#" + "reload_completed" + [(const_int 0)] + { + rtx lab = PATTERN (gen_call_site ()); ++ rtx scr = gen_rtx_REG (Pmode, R1_REG); + +- sh_expand_sym_label2reg (operands[3], operands[1], lab, false); +- emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3], ++ sh_expand_sym_label2reg (scr, operands[1], lab, false); ++ emit_call_insn (gen_call_valuei_pcrel (operands[0], scr, + operands[2], copy_rtx (lab))); + DONE; + } +@@ -6873,7 +6968,7 @@ + [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "")) + (match_operand 1 "" "")) + (use (reg:SI FPSCR_MODES_REG)) +- (clobber (match_scratch:SI 2 "=&k")) ++ (clobber (reg:SI R3_REG)) + (return)] + "TARGET_SH2 && !TARGET_FDPIC" + "#" +@@ -6881,10 +6976,11 @@ + [(const_int 0)] + { + rtx lab = PATTERN (gen_call_site ()); ++ rtx scr = gen_rtx_REG (Pmode, R3_REG); + rtx call_insn; + +- sh_expand_sym_label2reg (operands[2], operands[0], lab, true); +- call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1], ++ sh_expand_sym_label2reg (scr, operands[0], lab, true); ++ call_insn = emit_call_insn (gen_sibcalli_pcrel (scr, operands[1], + copy_rtx (lab))); + SIBLING_CALL_P (call_insn) = 1; + DONE; +@@ -6900,7 +6996,7 @@ + (match_operand 1)) + (use (reg:SI FPSCR_MODES_REG)) + (use (reg:SI PIC_REG)) +- (clobber (match_scratch:SI 2 "=k")) ++ (clobber (reg:SI R1_REG)) + (return)] + "TARGET_SH2 && TARGET_FDPIC" + "#" +@@ -6908,9 +7004,10 @@ + [(const_int 0)] + { + rtx lab = PATTERN (gen_call_site ()); ++ rtx scr = gen_rtx_REG (Pmode, R1_REG); + +- sh_expand_sym_label2reg (operands[2], operands[0], lab, true); +- rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1], ++ sh_expand_sym_label2reg (scr, operands[0], lab, true); ++ rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (scr, operands[1], + copy_rtx (lab))); + SIBLING_CALL_P (i) = 1; + DONE; +-- +2.45.2 + diff -Nru gcc15-new4/gcc-snapshot-20240829/debian/rules.defs gcc15-new3/gcc-snapshot-20240829/debian/rules.defs --- gcc15-new4/gcc-snapshot-20240829/debian/rules.defs 2024-08-29 12:12:59.000000000 +0200 +++ gcc15-new3/gcc-snapshot-20240829/debian/rules.defs 2024-09-14 10:19:51.220929851 +0200 @@ -754,7 +754,7 @@ # FIXME: compiler bug # m68k: PR 95381 -jit_no_cpus := ia64 +jit_no_cpus := ia64 sh4 ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(jit_no_cpus))) with_jit := disabled for cpu $(DEB_TARGET_ARCH_CPU) diff -Nru gcc15-new4/gcc-snapshot-20240829/debian/rules.patch gcc15-new3/gcc-snapshot-20240829/debian/rules.patch --- gcc15-new4/gcc-snapshot-20240829/debian/rules.patch 2024-08-20 11:26:06.000000000 +0200 +++ gcc15-new3/gcc-snapshot-20240829/debian/rules.patch 2024-09-13 18:52:32.274639593 +0200 @@ -183,6 +183,8 @@ ia64-disable-selective-scheduling \ libstdc++-pythondir \ gcc-verbose-lto-link \ + sh-lra-support \ + sh-enable-lra \ ifeq ($(with_ada),yes) debian_patches += \