From dea3680e796112da20e1f1ca6f1fbc9c0ea448d2 Mon Sep 17 00:00:00 2001 From: Alex Smith Date: Wed, 14 May 2014 15:31:34 +0100 Subject: [PATCH 05/12] MIPS: octeon: Add little endian structure/bitfield definitions This patch adds little endian versions of various hardware and boot loader structures and bitfields which are needed for a kernel to function correctly in little endian mode on Octeon. Signed-off-by: Alex Smith --- arch/mips/cavium-octeon/executive/cvmx-l2c.c | 43 +++++ arch/mips/cavium-octeon/octeon_boot.h | 16 ++ arch/mips/include/asm/octeon/cvmx-address.h | 68 +++++++ arch/mips/include/asm/octeon/cvmx-bootinfo.h | 55 ++++++ arch/mips/include/asm/octeon/cvmx-bootmem.h | 14 +- arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 11 ++ arch/mips/include/asm/octeon/cvmx-l2c.h | 9 + arch/mips/include/asm/octeon/cvmx-packet.h | 8 + arch/mips/include/asm/octeon/cvmx-pko.h | 31 ++++ arch/mips/include/asm/octeon/cvmx-pow.h | 247 ++++++++++++++++++++++++++ arch/mips/include/asm/octeon/cvmx-wqe.h | 68 +++++++ arch/mips/include/asm/octeon/octeon.h | 87 +++++++-- 12 files changed, 645 insertions(+), 12 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index 42e38c3..8f653ea 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -518,6 +518,7 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len) */ union __cvmx_l2c_tag { uint64_t u64; +#ifdef __BIG_ENDIAN_BITFIELD struct cvmx_l2c_tag_cn50xx { uint64_t reserved:40; uint64_t V:1; /* Line valid */ @@ -558,6 +559,48 @@ union __cvmx_l2c_tag { uint64_t U:1; /* Use, LRU eviction */ uint64_t addr:16; /* Phys mem addr (33..18) */ } cn58xx; +#else /* __BIG_ENDIAN_BITFIELD */ + struct cvmx_l2c_tag_cn50xx { + uint64_t addr:20; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:40; + } cn50xx; + struct cvmx_l2c_tag_cn30xx { + uint64_t addr:19; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:41; + } cn30xx; + struct cvmx_l2c_tag_cn31xx { + uint64_t addr:18; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:42; + } cn31xx; + struct cvmx_l2c_tag_cn38xx { + uint64_t addr:17; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:43; + } cn38xx; + struct cvmx_l2c_tag_cn58xx { + uint64_t addr:16; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:44; + } cn58xx; +#endif /* __BIG_ENDIAN_BITFIELD */ struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ }; diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h index 7b066bb..060a9f4 100644 --- a/arch/mips/cavium-octeon/octeon_boot.h +++ b/arch/mips/cavium-octeon/octeon_boot.h @@ -37,6 +37,7 @@ struct boot_init_vector { /* similar to bootloader's linux_app_boot_info but without global data */ struct linux_app_boot_info { +#ifdef __BIG_ENDIAN uint32_t labi_signature; uint32_t start_core0_addr; uint32_t avail_coremask; @@ -49,6 +50,21 @@ struct linux_app_boot_info { uint32_t compact_flash_common_base_addr; uint32_t compact_flash_attribute_base_addr; uint32_t led_display_base_addr; +#else /* __BIG_ENDIAN */ + uint32_t start_core0_addr; + uint32_t labi_signature; + uint32_t pci_console_active; + uint32_t avail_coremask; + uint32_t pad; + uint32_t icache_prefetch_disable; + uint64_t InitTLBStart_addr; + uint32_t cur_exception_base; + uint32_t start_app_addr; + uint32_t compact_flash_common_base_addr; + uint32_t no_mark_private_data; + uint32_t led_display_base_addr; + uint32_t compact_flash_attribute_base_addr; +#endif /* __BIG_ENDIAN */ }; /* If not to copy a lot of bootloader's structures diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h index e2d874e..c36f75a 100644 --- a/arch/mips/include/asm/octeon/cvmx-address.h +++ b/arch/mips/include/asm/octeon/cvmx-address.h @@ -104,6 +104,8 @@ typedef enum { typedef union { uint64_t u64; + +#ifdef __BIG_ENDIAN_BITFIELD /* mapped or unmapped virtual address */ struct { uint64_t R:2; @@ -202,7 +204,73 @@ typedef union { uint64_t didspace:24; uint64_t unused:40; } sfilldidspace; +#else /* __BIG_ENDIAN_BITFIELD */ + struct { + uint64_t offset:62; + uint64_t R:2; + } sva; + + struct { + uint64_t offset:31; + uint64_t zeroes:33; + } suseg; + + struct { + uint64_t offset:29; + uint64_t sp:2; + uint64_t ones:33; + } sxkseg; + + struct { + uint64_t pa:49; + uint64_t mbz:10; + uint64_t cca:3; + uint64_t R:2; + } sxkphys; + + struct { + uint64_t offset:36; + uint64_t unaddr:4; + uint64_t did:8; + uint64_t is_io:1; + uint64_t mbz:15; + } sphys; + + struct { + uint64_t offset:36; + uint64_t unaddr:4; + uint64_t zeroes:24; + } smem; + + /* physical IO address */ + struct { + uint64_t offset:36; + uint64_t unaddr:4; + uint64_t did:8; + uint64_t is_io:1; + uint64_t mbz:13; + uint64_t mem_region:2; + } sio; + struct { + uint64_t addr:13; + cvmx_add_win_dec_t csrdec:2; + uint64_t ones:49; + } sscr; + + struct { + uint64_t addr:7; + uint64_t type:3; + uint64_t unused2:3; + uint64_t csrdec:2; + uint64_t ones:49; + } sdma; + + struct { + uint64_t unused:40; + uint64_t didspace:24; + } sfilldidspace; +#endif /* __BIG_ENDIAN_BITFIELD */ } cvmx_addr_t; /* These macros for used by 32 bit applications */ diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 13c3bbb..207a952 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -53,6 +53,7 @@ * to 0. */ struct cvmx_bootinfo { +#ifdef __BIG_ENDIAN uint32_t major_version; uint32_t minor_version; @@ -123,6 +124,60 @@ struct cvmx_bootinfo { */ uint64_t fdt_addr; #endif +#else /* __BIG_ENDIAN */ + /* + * Little-Endian: When the CPU mode is switched to + * little-endian, the view of the structure has some of the + * fields swapped. + */ + uint32_t minor_version; + uint32_t major_version; + + uint64_t stack_top; + uint64_t heap_base; + uint64_t heap_end; + uint64_t desc_vaddr; + + uint32_t stack_size; + uint32_t exception_base_addr; + + uint32_t core_mask; + uint32_t flags; + + uint32_t phy_mem_desc_addr; + uint32_t dram_size; + + uint32_t eclock_hz; + uint32_t debugger_flags_base_addr; + + uint32_t reserved0; + uint32_t dclock_hz; + + uint8_t reserved3; + uint8_t reserved2; + uint16_t reserved1; + uint8_t board_rev_minor; + uint8_t board_rev_major; + uint16_t board_type; + + char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; + uint8_t mac_addr_base[6]; + uint8_t mac_addr_count; + uint8_t pad[5]; + +#if (CVMX_BOOTINFO_MIN_VER >= 1) + uint64_t compact_flash_common_base_addr; + uint64_t compact_flash_attribute_base_addr; + uint64_t led_display_base_addr; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 2) + uint32_t config_flags; + uint32_t dfa_ref_clock_hz; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 3) + uint64_t fdt_addr; +#endif +#endif /* __BIG_ENDIAN */ }; #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h index 352f1dc..083a27f 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h @@ -95,6 +95,7 @@ struct cvmx_bootmem_named_block_desc { * positions for backwards compatibility. */ struct cvmx_bootmem_desc { +#ifdef __BIG_ENDIAN /* spinlock to control access to list */ uint32_t lock; /* flags for indicating various conditions */ @@ -120,7 +121,18 @@ struct cvmx_bootmem_desc { uint32_t named_block_name_len; /* address of named memory block descriptors */ uint64_t named_block_array_addr; - +#else /* __BIG_ENDIAN */ + uint32_t flags; + uint32_t lock; + uint64_t head_addr; + uint32_t minor_version; + uint32_t major_version; + uint64_t app_data_addr; + uint64_t app_data_size; + uint32_t named_block_name_len; + uint32_t named_block_num_blocks; + uint64_t named_block_array_addr; +#endif /* __BIG_ENDIAN */ }; /** diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h index 024a71b..5e35828 100644 --- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h +++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h @@ -124,6 +124,7 @@ typedef enum { } cvmx_cmd_queue_result_t; typedef struct { +#ifdef __BIG_ENDIAN_BITFIELD /* You have lock when this is your ticket */ uint8_t now_serving; uint64_t unused1:24; @@ -138,6 +139,16 @@ typedef struct { uint64_t pool_size_m1:13; /* Number of commands already used in buffer */ uint64_t index:13; +#else /* __BIG_ENDIAN_BITFIELD */ + uint32_t max_depth; + uint64_t unused1:24; + uint8_t now_serving; + uint64_t index:13; + uint64_t pool_size_m1:13; + uint64_t unused2:6; + uint64_t base_ptr_div128:29; + uint64_t fpa_pool:3; +#endif /* __BIG_ENDIAN_BITFIELD */ } __cvmx_cmd_queue_state_t; /** diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h index 11c0a8f..54a4f9a 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c.h @@ -53,12 +53,21 @@ union cvmx_l2c_tag { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved:28; uint64_t V:1; /* Line valid */ uint64_t D:1; /* Line dirty */ uint64_t L:1; /* Line locked */ uint64_t U:1; /* Use, LRU eviction */ uint64_t addr:32; /* Phys mem (not all bits valid) */ +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t addr:32; + uint64_t U:1; + uint64_t L:1; + uint64_t D:1; + uint64_t V:1; + uint64_t reserved:28; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; }; diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h index 38aefa1..b357be5 100644 --- a/arch/mips/include/asm/octeon/cvmx-packet.h +++ b/arch/mips/include/asm/octeon/cvmx-packet.h @@ -39,6 +39,7 @@ union cvmx_buf_ptr { void *ptr; uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* if set, invert the "free" pick of the overall * packet. HW always sets this bit to 0 on inbound * packet */ @@ -55,6 +56,13 @@ union cvmx_buf_ptr { uint64_t size:16; /* Pointer to the first byte of the data, NOT buffer */ uint64_t addr:40; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t addr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; }; diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h index f7d2a67..85078f1 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko.h +++ b/arch/mips/include/asm/octeon/cvmx-pko.h @@ -127,6 +127,7 @@ typedef struct { typedef union { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Must CVMX_IO_SEG */ uint64_t mem_space:2; /* Must be zero */ @@ -151,6 +152,17 @@ typedef union { uint64_t queue:9; /* Must be zero */ uint64_t reserved4:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved4:3; + uint64_t queue:9; + uint64_t port:6; + uint64_t reserved3:18; + uint64_t reserved2:4; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved:13; + uint64_t mem_space:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; } cvmx_pko_doorbell_address_t; @@ -160,6 +172,7 @@ typedef union { typedef union { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* * The size of the reg1 operation - could be 8, 16, * 32, or 64 bits. @@ -229,6 +242,24 @@ typedef union { uint64_t segs:6; /* Including L2, but no trailing CRC */ uint64_t total_bytes:16; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t total_bytes:16; + uint64_t segs:6; + uint64_t dontfree:1; + uint64_t ignore_i:1; + uint64_t ipoffp1:7; + uint64_t gather:1; + uint64_t rsp:1; + uint64_t wqp:1; + uint64_t n2:1; + uint64_t le:1; + uint64_t reg0:11; + uint64_t subone0:1; + uint64_t reg1:11; + uint64_t subone1:1; + uint64_t size0:2; + uint64_t size1:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; } cvmx_pko_command_word0_t; diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h index 4b4d0ec..f07bc7c 100644 --- a/arch/mips/include/asm/octeon/cvmx-pow.h +++ b/arch/mips/include/asm/octeon/cvmx-pow.h @@ -178,6 +178,7 @@ typedef enum { typedef union { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* * Don't reschedule this entry. no_sched is used for * CVMX_POW_TAG_OP_SWTAG_DESCH and @@ -217,6 +218,17 @@ typedef union { * CVMX_POW_TAG_OP_*_NSCHED */ uint64_t tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t tag:32; + uint64_t type:3; + uint64_t grp:4; + uint64_t qos:3; + uint64_t unused2:2; + cvmx_pow_tag_op_t op:4; + uint64_t index:13; + uint64_t unused:2; + uint64_t no_sched:1; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; } cvmx_pow_tag_req_t; @@ -230,6 +242,7 @@ typedef union { * Address for new work request loads (did<2:0> == 0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Mips64 address region. Should be CVMX_IO_SEG */ uint64_t mem_region:2; /* Must be zero */ @@ -247,12 +260,22 @@ typedef union { uint64_t wait:1; /* Must be zero */ uint64_t reserved_0_2:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved_0_2:3; + uint64_t wait:1; + uint64_t reserved_4_39:36; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_region:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } swork; /** * Address for loads to get POW internal status */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Mips64 address region. Should be CVMX_IO_SEG */ uint64_t mem_region:2; /* Must be zero */ @@ -282,12 +305,25 @@ typedef union { uint64_t get_wqp:1; /* Must be zero */ uint64_t reserved_0_2:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved_0_2:3; + uint64_t get_wqp:1; + uint64_t get_cur:1; + uint64_t get_rev:1; + uint64_t coreid:4; + uint64_t reserved_10_39:30; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_region:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } sstatus; /** * Address for memory loads to get POW internal state */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Mips64 address region. Should be CVMX_IO_SEG */ uint64_t mem_region:2; /* Must be zero */ @@ -314,12 +350,24 @@ typedef union { uint64_t get_wqp:1; /* Must be zero */ uint64_t reserved_0_2:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved_0_2:3; + uint64_t get_wqp:1; + uint64_t get_des:1; + uint64_t index:11; + uint64_t reserved_16_39:24; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_region:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } smemload; /** * Address for index/pointer loads */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Mips64 address region. Should be CVMX_IO_SEG */ uint64_t mem_region:2; /* Must be zero */ @@ -366,6 +414,17 @@ typedef union { uint64_t get_rmt:1; /* Must be zero */ uint64_t reserved_0_2:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved_0_2:3; + uint64_t get_rmt:1; + uint64_t get_des_get_tail:1; + uint64_t qosgrp:4; + uint64_t reserved_9_39:31; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_region:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } sindexload; /** @@ -377,6 +436,7 @@ typedef union { * available.) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Mips64 address region. Should be CVMX_IO_SEG */ uint64_t mem_region:2; /* Must be zero */ @@ -387,6 +447,13 @@ typedef union { uint64_t did:8; /* Must be zero */ uint64_t reserved_0_39:40; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t reserved_0_39:40; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_region:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } snull_rd; } cvmx_pow_load_addr_t; @@ -401,6 +468,7 @@ typedef union { * Response to new work request loads */ struct { +#ifdef __BIG_ENDIAN_BITFIELD /* * Set when no new work queue entry was returned. * * If there was de-scheduled work, the HW will @@ -419,12 +487,18 @@ typedef union { uint64_t reserved_40_62:23; /* 36 in O1 -- the work queue pointer */ uint64_t addr:40; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t addr:40; + uint64_t reserved_40_62:23; + uint64_t no_work:1; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_work; /** * Result for a POW Status Load (when get_cur==0 and get_wqp==0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* Set when there is a pending non-NULL SWTAG or * SWTAG_FULL, and the POW entry has not left the list @@ -476,12 +550,32 @@ typedef union { * AND pend_desched_switch) are set. */ uint64_t pend_tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t pend_tag:32; + uint64_t pend_type:2; + uint64_t reserved_34_35:2; + uint64_t pend_grp:4; + uint64_t pend_index:11; + uint64_t reserved_51:1; + uint64_t pend_nosched_clr:1; + uint64_t pend_null_rd:1; + uint64_t pend_new_work_wait:1; + uint64_t pend_new_work:1; + uint64_t pend_nosched:1; + uint64_t pend_desched_switch:1; + uint64_t pend_desched:1; + uint64_t pend_switch_null:1; + uint64_t pend_switch_full:1; + uint64_t pend_switch:1; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus0; /** * Result for a POW Status Load (when get_cur==0 and get_wqp==1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* * Set when there is a pending non-NULL SWTAG or @@ -529,6 +623,23 @@ typedef union { uint64_t pend_grp:4; /* This is the wqp when pend_nosched_clr is set. */ uint64_t pend_wqp:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t pend_wqp:36; + uint64_t pend_grp:4; + uint64_t pend_index:11; + uint64_t reserved_51:1; + uint64_t pend_nosched_clr:1; + uint64_t pend_null_rd:1; + uint64_t pend_new_work_wait:1; + uint64_t pend_new_work:1; + uint64_t pend_nosched:1; + uint64_t pend_desched_switch:1; + uint64_t pend_desched:1; + uint64_t pend_switch_null:1; + uint64_t pend_switch_full:1; + uint64_t pend_switch:1; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus1; /** @@ -536,6 +647,7 @@ typedef union { * get_rev==0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* * Points to the next POW entry in the tag list when @@ -573,12 +685,23 @@ typedef union { * SWTAG_DESCHED). */ uint64_t tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t tag:32; + uint64_t tag_type:2; + uint64_t tail:1; + uint64_t head:1; + uint64_t grp:4; + uint64_t index:11; + uint64_t link_index:11; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus2; /** * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* * Points to the prior POW entry in the tag list when @@ -617,6 +740,16 @@ typedef union { * SWTAG_DESCHED). */ uint64_t tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t tag:32; + uint64_t tag_type:2; + uint64_t tail:1; + uint64_t head:1; + uint64_t grp:4; + uint64_t index:11; + uint64_t revlink_index:11; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus3; /** @@ -624,6 +757,7 @@ typedef union { * get_rev==0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* * Points to the next POW entry in the tag list when @@ -642,6 +776,13 @@ typedef union { * list entered on SWTAG_FULL). */ uint64_t wqp:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t wqp:36; + uint64_t grp:4; + uint64_t index:11; + uint64_t link_index:11; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus4; /** @@ -649,6 +790,7 @@ typedef union { * get_rev==1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; /* * Points to the prior POW entry in the tag list when @@ -669,12 +811,20 @@ typedef union { * list entered on SWTAG_FULL). */ uint64_t wqp:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t wqp:36; + uint64_t grp:4; + uint64_t index:11; + uint64_t revlink_index:11; + uint64_t reserved_62_63:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_sstatus5; /** * Result For POW Memory Load (get_des == 0 and get_wqp == 0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; /* * The next entry in the input, free, descheduled_head @@ -695,12 +845,22 @@ typedef union { uint64_t tag_type:2; /* The tag of the POW entry. */ uint64_t tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t tag:32; + uint64_t tag_type:2; + uint64_t tail:1; + uint64_t reserved_35:1; + uint64_t grp:4; + uint64_t next_index:11; + uint64_t reserved_51_63:13; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_smemload0; /** * Result For POW Memory Load (get_des == 0 and get_wqp == 1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; /* * The next entry in the input, free, descheduled_head @@ -712,12 +872,19 @@ typedef union { uint64_t grp:4; /* The WQP held in the POW entry. */ uint64_t wqp:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t wqp:36; + uint64_t grp:4; + uint64_t next_index:11; + uint64_t reserved_51_63:13; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_smemload1; /** * Result For POW Memory Load (get_des == 1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; /* * The next entry in the tag list connected to the @@ -740,12 +907,22 @@ typedef union { * is set. */ uint64_t pend_tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t pend_tag:32; + uint64_t pend_type:2; + uint64_t pend_switch:1; + uint64_t nosched:1; + uint64_t grp:4; + uint64_t fwd_index:11; + uint64_t reserved_51_63:13; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_smemload2; /** * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; /* * set when there is one or more POW entries on the @@ -791,12 +968,28 @@ typedef union { * the input Q list selected by qosgrp. */ uint64_t loc_tail:11; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t loc_tail:11; + uint64_t reserved_11:1; + uint64_t loc_head:11; + uint64_t reserved_23:1; + uint64_t loc_one:1; + uint64_t loc_val:1; + uint64_t free_tail:11; + uint64_t reserved_37:1; + uint64_t free_head:11; + uint64_t reserved_49:1; + uint64_t free_one:1; + uint64_t free_val:1; + uint64_t reserved_52_63:12; +#endif /* __BIG_ENDIAN_BITFIELD */ } sindexload0; /** * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; /* * set when there is one or more POW entries on the @@ -843,12 +1036,28 @@ typedef union { * head on the descheduled list selected by qosgrp. */ uint64_t des_tail:11; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t des_tail:11; + uint64_t reserved_11:1; + uint64_t des_head:11; + uint64_t reserved_23:1; + uint64_t des_one:1; + uint64_t des_val:1; + uint64_t nosched_tail:11; + uint64_t reserved_37:1; + uint64_t nosched_head:11; + uint64_t reserved_49:1; + uint64_t nosched_one:1; + uint64_t nosched_val:1; + uint64_t reserved_52_63:12; +#endif /* __BIG_ENDIAN_BITFIELD */ } sindexload1; /** * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; /* * Set when this DRAM list is the current head @@ -877,6 +1086,13 @@ typedef union { * qosgrp. */ uint64_t rmt_head:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t rmt_head:36; + uint64_t rmt_one:1; + uint64_t rmt_val:1; + uint64_t rmt_is_head:1; + uint64_t reserved_39_63:25; +#endif /* __BIG_ENDIAN_BITFIELD */ } sindexload2; /** @@ -884,6 +1100,7 @@ typedef union { * 1/get_des_get_tail == 1) */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; /* * set when this DRAM list is the current head @@ -912,12 +1129,20 @@ typedef union { * qosgrp. */ uint64_t rmt_tail:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t rmt_tail:36; + uint64_t rmt_one:1; + uint64_t rmt_val:1; + uint64_t rmt_is_head:1; + uint64_t reserved_39_63:25; +#endif /* __BIG_ENDIAN_BITFIELD */ } sindexload3; /** * Response to NULL_RD request loads */ struct { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t unused:62; /* of type cvmx_pow_tag_type_t. state is one of the * following: @@ -928,6 +1153,10 @@ typedef union { * - CVMX_POW_TAG_TYPE_NULL_NULL */ uint64_t state:2; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t state:2; + uint64_t unused:62; +#endif /* __BIG_ENDIAN_BITFIELD */ } s_null_rd; } cvmx_pow_tag_load_resp_t; @@ -962,6 +1191,7 @@ typedef union { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* Memory region. Should be CVMX_IO_SEG in most cases */ uint64_t mem_reg:2; uint64_t reserved_49_61:13; /* Must be zero */ @@ -971,6 +1201,14 @@ typedef union { uint64_t reserved_36_39:4; /* Must be zero */ /* Address field. addr<2:0> must be zero */ uint64_t addr:36; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t addr:36; + uint64_t reserved_36_39:4; + uint64_t did:8; + uint64_t is_io:1; + uint64_t reserved_49_61:13; + uint64_t mem_reg:2; +#endif /* __BIG_ENDIAN_BITFIELD */ } stag; } cvmx_pow_tag_store_addr_t; @@ -981,6 +1219,7 @@ typedef union { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* * the (64-bit word) location in scratchpad to write * to (if len != 0) @@ -994,6 +1233,14 @@ typedef union { /* if set, don't return load response until work is available */ uint64_t wait:1; uint64_t unused2:3; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t unused2:3; + uint64_t wait:1; + uint64_t unused:36; + uint64_t did:8; + uint64_t len:8; + uint64_t scraddr:8; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; } cvmx_pow_iobdma_store_t; diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h index aa0d3d0..25e80f1 100644 --- a/arch/mips/include/asm/octeon/cvmx-wqe.h +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h @@ -55,6 +55,7 @@ typedef union { uint64_t u64; +#ifdef __BIG_ENDIAN_BITFIELD /* Use this struct if the hardware determines that the packet is IP */ struct { /* HW sets this to the number of buffers used by this packet */ @@ -297,7 +298,59 @@ typedef union { /* type is cvmx_pip_err_t (union, so can't use directly */ uint64_t err_code:8; } snoip; +#else /* __BIG_ENDIAN_BITFIELD */ + struct { + uint64_t err_code:8; + uint64_t rcv_error:1; + uint64_t not_IP:1; + uint64_t is_mcast:1; + uint64_t is_bcast:1; + uint64_t IP_exc:1; + uint64_t is_frag:1; + uint64_t L4_error:1; + uint64_t software:1; + uint64_t is_v6:1; + uint64_t dec_ipsec:1; + uint64_t tcp_or_udp:1; + uint64_t dec_ipcomp:1; + uint64_t unassigned2:8; + uint64_t pr:4; + uint64_t vlan_id:12; + uint64_t vlan_cfi:1; + uint64_t unassigned:1; + uint64_t vlan_stacked:1; + uint64_t vlan_valid:1; + uint64_t ip_offset:8; + uint64_t bufs:8; + } s; + + struct { + uint64_t unused2:32; + uint64_t vlan:16; + uint64_t unused1:16; + } svlan; + struct { + uint64_t err_code:8; + uint64_t rcv_error:1; + uint64_t not_IP:1; + uint64_t is_mcast:1; + uint64_t is_bcast:1; + uint64_t is_arp:1; + uint64_t is_rarp:1; + uint64_t unassigned3:1; + uint64_t software:1; + uint64_t unassigned2:12; + uint64_t pr:4; + uint64_t vlan_id:12; + uint64_t vlan_cfi:1; + uint64_t unassigned:1; + uint64_t vlan_stacked:1; + uint64_t vlan_valid:1; + uint64_t unused:8; + uint64_t bufs:8; + } snoip; +#endif } cvmx_pip_wqe_word2; /** @@ -312,6 +365,7 @@ typedef struct { * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ +#ifdef __BIG_ENDIAN_BITFIELD /** * raw chksum result generated by the HW */ @@ -327,12 +381,18 @@ typedef struct { * (Only 36 bits used in Octeon 1) */ uint64_t next_ptr:40; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t next_ptr:40; + uint8_t unused; + uint16_t hw_chksum; +#endif /* __BIG_ENDIAN_BITFIELD */ /***************************************************************** * WORD 1 * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ +#ifdef __BIG_ENDIAN_BITFIELD /** * HW sets to the total number of bytes in the packet */ @@ -359,6 +419,14 @@ typedef struct { * the synchronization/ordering tag */ uint64_t tag:32; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t tag:32; + uint64_t tag_type:3; + uint64_t grp:4; + uint64_t qos:3; + uint64_t ipprt:6; + uint64_t len:16; +#endif /* __BIG_ENDIAN_BITFIELD */ /** * WORD 2 HW WRITE: the following 64-bits are filled in by diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index d781f9e..41b90f6 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -58,6 +58,7 @@ extern void octeon_io_clk_delay(unsigned long); #define OCTOEN_SERIAL_LEN 20 struct octeon_boot_descriptor { +#ifdef __BIG_ENDIAN /* Start of block referenced by assembly code - do not change! */ uint32_t desc_version; uint32_t desc_size; @@ -74,17 +75,6 @@ struct octeon_boot_descriptor { /* Argc count for application. */ uint32_t argc; uint32_t argv[OCTEON_ARGV_MAX_ARGS]; - -#define BOOT_FLAG_INIT_CORE (1 << 0) -#define OCTEON_BL_FLAG_DEBUG (1 << 1) -#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) - /* If set, use uart1 for console */ -#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) - /* If set, use PCI console */ -#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) - /* Call exit on break on serial port */ -#define OCTEON_BL_FLAG_BREAK (1 << 5) - uint32_t flags; uint32_t core_mask; /* DRAM size in megabyes. */ @@ -109,11 +99,54 @@ struct octeon_boot_descriptor { uint8_t mac_addr_base[6]; uint8_t mac_addr_count; uint64_t cvmx_desc_vaddr; +#else /* __BIG_ENDIAN */ + uint32_t desc_size; + uint32_t desc_version; + uint64_t stack_top; + uint64_t heap_base; + uint64_t heap_end; + uint64_t entry_point; + uint64_t desc_vaddr; + uint32_t stack_size; + uint32_t exception_base_addr; + uint32_t argc; + uint32_t heap_size; + uint32_t argv[OCTEON_ARGV_MAX_ARGS]; + uint32_t core_mask; + uint32_t flags; + uint32_t phy_mem_desc_addr; + uint32_t dram_size; + uint32_t eclock_hz; + uint32_t debugger_flags_base_addr; + uint32_t spi_clock_hz; + uint32_t dclock_hz; + uint8_t chip_rev_minor; + uint8_t chip_rev_major; + uint16_t chip_type; + uint8_t board_rev_minor; + uint8_t board_rev_major; + uint16_t board_type; + + uint64_t unused1[4]; /* Not even filled in by bootloader. */ + + uint64_t cvmx_desc_vaddr; +#endif /* __BIG_ENDIAN */ }; +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) + /* If set, use uart1 for console */ +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) + /* If set, use PCI console */ +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) + /* Call exit on break on serial port */ +#define OCTEON_BL_FLAG_BREAK (1 << 5) + union octeon_cvmemctl { uint64_t u64; struct { +#ifdef __BIG_ENDIAN_BITFIELD /* RO 1 = BIST fail, 0 = BIST pass */ uint64_t tlbbist:1; /* RO 1 = BIST fail, 0 = BIST pass */ @@ -206,6 +239,38 @@ union octeon_cvmemctl { /* R/W Size of local memory in cache blocks, 54 (6912 * bytes) is max legal value. */ uint64_t lmemsz:6; +#else /* __BIG_ENDIAN_BITFIELD */ + uint64_t lmemsz:6; + uint64_t cvmsegenau:1; + uint64_t cvmsegenas:1; + uint64_t cvmsegenak:1; + uint64_t reserved2:2; + uint64_t wbthresh:4; + uint64_t istrnol2:1; + uint64_t wbfltime:3; + uint64_t mclkalwys:1; + uint64_t csrckalwys:1; + uint64_t didtto:2; + uint64_t nomerge:1; + uint64_t allsyncw:1; + uint64_t xkioenau:1; + uint64_t xkioenas:1; + uint64_t xkmemenau:1; + uint64_t xkmemenas:1; + uint64_t diswbfst:1; + uint64_t dissyncws:1; + uint64_t syncwsmarked:1; + uint64_t iobdmascrmsb:2; + uint64_t dismrgclrwbto:1; + uint64_t dismarkwblongto:1; + uint64_t reserved:22; + uint64_t wbfbist:1; + uint64_t ptgbist:1; + uint64_t dcmbist:1; + uint64_t l1dbist:1; + uint64_t l1cbist:1; + uint64_t tlbbist:1; +#endif /* __BIG_ENDIAN_BITFIELD */ } s; }; -- 2.1.0